@Tim Edwards the script you gave me for parasitic extraction flattens the design:

set project [lindex $argv $argc-1]
load $project.mag
flatten tt_um_flat
load tt_um_flat
select top cell
cellname delete $project
cellname rename tt_um_flat ${project}_parax
extract all
ext2sim labels on
ext2sim
extresist tolerance 10
extresist
ext2spice lvs
ext2spice cthresh 0
ext2spice extresist on
ext2spice
ext2spice -d -o $project.sim.spice
quit -noprompt

Flattening is necessary for parasitic resistor extraction. magic cannot calculate parasitic resistances across hierarchies.

thanks

I believe you can extract parasitic capacitance hierarchically, but there may be discrepancies if there is a lot of overlap. I may be wrong though.

Slight correction: Magic probably doesn't correctly do full parasitic extraction across hierarchy. I worked on it a bit a few years ago but I'm pretty sure there are errors that haven't been addressed. The parasitic capacitance is done completely within the standard extraction, although after breaking up a network with resistances, the parasitic capacitances have to be distributed across that network. In the script above, you are running

ext2spice

twice. Also, the second time you are using

-d

, which has been deprecated. I also wouldn't use "sim" in the name---you can simulate any valid netlist; I generally prefer "rcx" to be clear that the netlist has full R-C parasitics, although the way I actually do it is to just keep the default name and move it to a directory called "netlist/rcx". But anyway, following your style there, I would suggest

ext2spice -o ${project}.sim.spice

and remove the line with

ext2spice

by itself. Also, usually I go for a

cthresh

value of 0.1 so that magic doesn't output a bunch of ridiculously tiny capacitors. The impact on simulation will be negligible.