@Mitch Bailey @Tim Edwardsi passed the LVS for an unflatten layout, but when I made it flatten the LVS is not passing. Could you please help me?

Your

core_flat.spice

file has a black-box entry for the ReRAM cell, but the

.ends

statement is at the end of the file, so the entire flattened circuit has (incorrectly) been put inside the ReRAM cell. I don't know how it got that way.

@Tim Edwards thank you and i tried to remove the black box entry for reram run , i tried to put the .ends just after blackbox entry for reram but it failed LVS and later LVS pass Thank you

@Rafeeq Khan Mohammed Can you share your repo?

@Mitch Bailey I did not made my repository and now LVS is passed thank you If required ? I can share my files here . Thank you

Congratulations! If LVS is passing, you don’t need to share anything else.