Hi all, Currently I am synthesizing my design, unfortunately at step 33 STA my design reports some timing violations. Can someone help me solve this problem? tong is leaving the parameter MAX_FANOUT: 16.

Can you share your config.json file?

@Mitch Bailey This is my config file

@Nam Nguyễn Hồ Giang I wonder if

"SYNTH_BUFFERING": 1,

would make a difference. Or do you not want buffering?

@Mitch Bailey Because adding buffer will increase the area and cell count so I turn it off. Unfortunately it can cause my timing to fail. That's a hint for me to try running again.

I’m not an expert on timing, but excessive fanout will add capacitance to the nodes and therefore increase the time necessary for signal propagation. This can lead to slew errors and timing errors. If you have a repeating layout, you might try to add buffer blocks in verilog on critical nets or nets with high fanout.