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Hello. I'm doing LVS to verify gf180mcuD standard cell(flip-flop and inverter) in Klayout.
Howerver, It doesn't seem to read stadard cell spice code as belows.
Could you give me any advice?

<@U04TWKZ0JSU> Can you share your gds and schematic generated spice file (as opposed to just a screen shot)?

dffqnq_1.gds

dffqnq_1.spice

<@U017X0NM2E7> but, .include directory should be changed in other's computer

The klayout rules don’t label nwel or psub.

Does it means that DVNW, DVPW don't have any seperation just VDD and  VSS?

It means that it won’t work unless there’s a tap cell to connect nwell to VDD and psub to VSS. My local klayout is not working as I wished. I’ll look into it more in the morning.

dffqnq.png

<@U04TWKZ0JSU> These are the problems I’m seeing so far.
1. The spice library contains `X` devices, but klayout is extracting `M` devices. There is a cdl library that has `M` devices.
2. The LVS rules do not connect text to psub or nwell.
3. klayout is extracting the mosfets as 3.3V devices while the cdl defines them as 5V devices.
4. The layout is the same as dffq_1 but the source netlist has dffq_1 and an inverter.
5. There is no `nQ` port in the layout.
6. The nfet/pfet driving net2 from the clocked inverter are slightly longer 0.605/0.505 than the schematic 0.6/0.5.

<@U017X0NM2E7>
Thanks for your help.
1 -&gt; I replaced spice with cdl as below. but it brought an error in Klayout TT
3 -&gt; how to extract mosfets as 3.3V and 5V devices both in case of simulating analog + digital part
4, 5 -&gt; I got it
6 -&gt; I just used standard cell provided by gf180mcuD sets. Should I modify layout of nfet/pfet driving net2?

1. The diodes are bad in the cdl (according to klayout). I just used cells that I needed.
3. I think there’s a recognition layer that differentiates between 3.3V and 5V. Can you find it by looking at the rule file?
6. You can change the layout or the schematic.

these are mos_derivations and mos_extraction file of "gf180mcu -&gt; rule_decks"

<@U04TWKZ0JSU> What’s the difference between `ngate_lv_n_dw` and `ngate_5v_n_dw`?

<@U017X0NM2E7>
it may be "differnt layer" which divide 3.3V/5V cell as you said.
I looked at the original layout of standard cell  and finally I got  a mistake I did when I imported cell.
Contrary to the first layout picture(which I did use), the original cell has another layers like "Dualgate 55/0" and "PR_bndry0/0".
I deliberately deleted these layers because they seemed not to make any difference.
Thus, DRC and LVS passed.
Thank you, David.