I just banged my head for hours against a non simulating post layout circuit, and it was because the extracted ports got re-ordered. The LVS extraction keeps the ports ordered by the port number in the mag file, but my script for extraction for simulation seems to put them in an order uninfluenced by the port numbering. Any idea why or how to stop it from happening?

Historically, I've come up with two ways to deal with this problem. The first was that I used CACE with a special format for pins to create a call to a subcircuit which CACE would then fix the order of the pins; that means you never have to worry about pin order, but it only works with CACE. The other thing is to make sure that the schematic capture tool always generates the pin order the same way (which xschem does, now); then, as long as the schematic is imported into the layout (using magic's "Import SPICE" function, then the layout inherits the port order that was in the schematic. If you don't use that method, you need to ensure that the port order in the layout matches (by index) the port order in the schematic-captured netlist.

@Matt Venn I use this https://github.com/wulffern/tech_sky130A/blob/main/script/fixlpe to copy the xschem pin order into the lpe netlist.