Simulation reports extremely low (9e-18 amps) leakage through pfet_g5v0d10v5 when VGS is positive. T...
l
Simulation reports extremely low (9e-18 amps) leakage through pfet_g5v0d10v5 when VGS is positive. Think this is accurate at all? (PDK docs say to keep VGS negative. Raw data indeed seems to always have VGS negative. Any intuition I can use? This is for a low-leakage switched capacitor.)
b
It's not accurate. Gate-induced drain leakage (GIDL) will lead to higher numbers in reality. As a rule of thumb, look at the leakage for VGS~0. Making VGS more positive for a PMOS will still give you the same current (or slightly higher).
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l
Much appreciated. Is there any easy/systematic way to learn such things?
b
I don't know abut an easy way, but taking a course on MOS device physics would do.
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l
Actually, the simulation also reports attoamp currents when everything is in range. Is this also erroneous?
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b
Most likely, yes. You saw our other thread where we talked about gm/ID being off for the PMOS devices. These two issues are links, since gm/ID is just the log-slope of the current. Try the NMOS, it may give more realistic numbers.
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l
Hmm still quite tiny for pretty reasonable voltages.
b
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l
Thanks I don't understand why it's A/um. Length and width are fixed at 10,0.13?
b
10^-10 A/um = 100pA/um. The right column just documents the device that was used in the measurement. For that 10um device, the leakage current would be 1nA.
l
Yes you multiply by width, and length doesn't matter for off-leakage? Please excuse my ignorance
I would've expected
leakage = 10^-10 * W / L
Although now I'm confused about whether this is leakage from opposite side of transistor or from bulk No worries if you've educated me enough already šŸ˜†
b
Leakage depends on L. But they measured it for L=0.13um and it was 100pA per width in microns. You cannot simply throw L into that calculation; that dependency is complex and would require another measurement in this case.
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c
@Boris Murmann, just as sanity check: Does G[ate]I[nduced]D[rain]L[eakage] affect Ids, or could it possibly cause a bulk-to-drain current? I got seriously stuck with some simulations where I got an unexpected exponential current across a reverse biased bulk diode. • Is there any chance at all that this is real and not just bad modeling? • If it's a bad model, which parameters would I want to tweak to get rid of the bulk current?
b
@Christoph Maier Could be real, due to SCBE?
c
Bernhard Boser's presentation goes way back …