for lvs, do transistors have to be the right way round? I have this

XM1 osc_a osc_b left_cap VSS sky130_fd_pr__nfet_01v8

for schematic and this

XXM1 osc_a VSUBS osc_b left_cap sky130_fd_pr__nfet_01v8_L9BG78

for layout.

The order in netlist is Drain - Gate - Source - Body, In general "normal" transistors are symmetrical, source and drain can be swapped. Some high voltage or "special" transistors have different shapes / diffusion profiles on the drain to handle (for example) high voltages or other features, so these are not symmetrical.

┌────┬─────┬─────┬────────┬────────┐
│Dev │D    │G    │S       │B       │
╞════╪═════╪═════╪════════╪════════╡
│XM1 │osc_a│osc_b│left_cap│VSS     │
├────┼─────┼─────┼────────┼────────┤
│XXM1│osc_a│VSUBS│osc_b   │left_cap│
└────┴─────┴─────┴────────┴────────┘

Looks there are some misconnections if these two transistors are supposed to match. The second transistor body connection is not to VSS as it normally should.

In principle, the drain will be tied to a power rail and the source will be on the opposite side. Physically, it doesn't make any difference because the source and drain of the transistor are identical. In LVS, the netgen setup file specifies that source and drain of FET devices are permutable, so that it doesn't matter which is which (same with resistor ends, but not with things that are physically different, like capacitor top and bottom).

thanks, very helpful

@Matt Venn there is a

VSUBS

net in the extracted layout. This is most likely the substrate connection. I there a ptap connected in your layout? If you’re extracting from gds, you can use

flatglob sky130_fd_pr__*[A-Z]*

to flatten any pcells before extraction. That might make the netlist easier to read. I use

ext2spice merge conservative

to combine parallel devices too.

I don't think flattening parameterized cells is all that helpful, since they're going to be flattened right away in netgen because they don't match anything in the schematic. The VSUBS, though, being separate from VSS, is a clear indicator that there is no substrate contact in the design (which would connect VSS to VSUBS).

@Tim Edwards

I don’t think flattening parameterized cells is all that helpful, since they’re going to be flattened right away in netgen because they don’t match anything in the schematic.

I agree that if the layout and schematic match, it (generally) makes no difference whether the parameterized cells are flattened or not. (I’ve seen cases where the parameterized cell doesn’t extract a pin which can cause problems). However, when the designs don’t match and I have to look at the extracted netlist, I find it much easier to see the connections of transistors directly than trying to remember what order they were extracted in for each parameterized cell (but that may be age related 😄).

yeah. me too - the seemingly random port order really makes it harder

flatglob

goes in the extract script before

gds read

(note that this won’t work with

gds readonly

).

thanks