@Tim Edwards @jeffdi Some time back, i seen some discussion on MPW shuttle more than 44 gpio ports, i remember it like 144 Pins ? Is there is any progress/plan on this ? Which MPW shuttle will have support this ?

My thoughts. I would like an option with more pins too. However I can see why this might be challenging for eFabless. In order to get more pins you either significantly increase the die size (hence costs) or move to a more advanced packaging option (flip chip?) which will also increase costs. Increasing costs will probably imply lower demand for those shuttles. Maybe it could be a once a year shuttle instead of every quarter? This is me simply thinking out loud.

@Dinesh A: Yes. It's the next-generation Caravel, and a test version of it is scheduled to go out on the upcoming June shuttle, with availability for users some time after that. Since we have to validate the test chip, I'm assuming that's going to be early 2025. The padframe has 128 pins, by the way, with 80 GPIOs, with a similar setup to the existing Caravel (so 8 GPIOs are dedicated to the processor, leaving 72 GPIOs for the end user).

Hi Tim, could we get a sneak preview of the specs? Things like die area and pin layout? What packaging options would be supported?

@Kauser Johar: There was a quick preview in the Chipalooza launch webinar (see the #chipalooza channel). I'm not sure how much detail can be ascertained from the slide. The die area is the same as Caravel. I just packed as many pads as I could fit into the padframe, including 16 over-voltage tolerant GPIO, a few analog pads, and a differential pad. Because there are no good QFN options at that pin count, we are expecting to package it in a 128-pin TQFP.

@Tim Edwards Is there is any plan to support it in openframe structure also; so that user get more Die area?

Yes, there will be an openframe structure.