Now I've got my LVS working, I'm trying to do post...
# analog-design
m
Now I've got my LVS working, I'm trying to do post layout simulation
1
I had to add - which I don't know what that means
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.param mc_mm_switch=1
.param mc_pr_switch=1
But it still has warnings and fails with
message has been deleted
The res_generic are from the conb cells
message has been deleted
which I think are being added by magic?
Is there another library I need to add for this to work?
but without an answer
And the PDK I'm using is installed by volare: volare/sky130/versions/78b7bc32ddb4b6f14f76883c2e2dc5b5de9d1cbc/sky130A
t
Whoa, whoa, back up. . .
extract do resistance
doesn't do what you think it does. In fact, it doesn't do anything because it's related to .sim files, not .spice files.
m
<screeetch>
1
t
There is a recipe for doing full R-C extraction floating around, but I have it memorized, to I'll add it here:
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load r2r
flatten r2r_flat
load r2r_flat
select top cell
cellname delete r2r
cellname rename r2r_flat r2r
extract all
ext2sim labels on
ext2sim
extresist tolerance 10
extresist
ext2spice lvs
ext2spice cthresh 0
ext2spice extresist on
ext2spice
Beware that this script flattens the cell and then renames the cell to the flattened version, so don't go save the flattened version back to disk, just quit after running this script.
m
thanks!
t
For simulation, you do not need to set
.param mc_mm_switch
and
.param mc_pr_switch
. Those are taken care of by the
.lib
statement. The 3rd argument to
.lib
is a section of the
.lib
file (
sky130.lib.spice
) to read and execute. That section defines the parameters. For the record,
mc_mm_switch
is a mismatch parameter (enables mismatch analysis by applying random variation to each component) and
mc_pr_switch
is a process variation parameter (enables monte carlo analysis by applying random variation to properties of the entire process).
m
thanks!
t
Actually, your extraction was more or less correct but hierarchical parasitic extraction is very unreliable so you need to do the flattning part.
1
Why
res_generic_po
isn't being found in simulation is probably an independent problem that will need to be tracked down. This seems like a PDK issue.
Doing
.lib sky130.lib.spice tt
should have included
$PDK_ROOT/sky130A/libs.tech/ngspice/sky130_fd_pr__model__r+c.model.spice
which should have at line 134:
.model sky130_fd_pr__res_generic_po  r tc1r=tc1rsgp  tc2r=tc2rsgpu   rsh=rp1   dw="-tol_poly/2-poly_dw/2" tnom=30
The original Sky130 PDK incorrectly commented out that line. The official PDK repository from Efabless fixes it.
1
m
it's commented out in my PDK.
which is installed with volare
new extraction seems to work
I uncomment the line in the pdk
but sim fails with hundreds of these:
adding those param lines lets the sim start
so I guess there is another issue with the PDK?
t
What version of the PDK does volare claim to be using? That particular problem was fixed in open_pdks early on, years ago.
m
volare/sky130/versions/78b7bc32ddb4b6f14f76883c2e2dc5b5de9d1cbc/sky130A
it's installed by the latest caravel_user_project Makefile using make setup - so anyone using recent PDK installed that way will have the same issue
t
That version is half a year and 94 commits out of date
m
hm
could be me
t
Even then, it should have been run through open_pdks and that resistor line should have been uncommented.
m
how would you recommend me install the pdk?
also, as a general question I want to do post layout sim, but the block is mixed signal with an openlane generated block which slows spice down a lot. Is there a way to just simulate part of the design?
t
Since a lot of people are using volare, I'd like to work out what went wrong with that, and why.
m
so you know, I templated caravel_user_project, then ran make setup
message has been deleted
message has been deleted
in caravel Makefile
but then in caravel_user_project makefile, it's set as
message has been deleted
so the caravel one is getting overridden
t
And the answer to your general question: You already looked at how to do co-simulation with iverilog running verilog code for stimulus generation. The other method to use when you have an internal digital block is xspice. There are two methods to xspice: One is to run yosys and synthesize to the small base set of predefined digital blocks understood by xspice. I don't particularly like that method, since it involves re-synthesizing and potentially introducing differences in the digital interface. The other method is to use my script
spi2xspice.py
from the "qflow" repository (opencircuitdesign.com) which uses a "generic" logic block I created for xspice which Holger Vogt integrated into the ngspice source. That creates an xspice block that is the equivalent of the low-level SPICE. Then you replace the SPICE subcircuit with the xspice one in the netlist.
1
m
could I remove the digital block in the spice file and drive the analog part with ngspice cosimulation?
really all I want is the parastics and resitances of the wiring, because I already have the sim of the analog block on its own
t
Well, that's where the problem of the parasitic extraction not working hierarchically will become a problem for efficient simulation. I might have to do some development on the parasitic extraction code so that it can handle extraction on a single hierarchical level and ignore subcells, or do that when subcells are abstracted.
1
That is development that definitely needs to get done.
🖖 1
You can try
extresist blackbox on
, which is supposed to do that. I have extremely low confidence that it will actually work.
c
Looks like the two of you (and maybe @Stefan Schippers) are the guys to watch among all the "looks ok but isn't, for some subtle reasons" flood of opinions (as opposed to fact) in the discussion forums. For the chipalooza, I want to go for the building block (Ibias for everyone else) that requires parasitic extraction and PVT/matching simulation first, i.e. goes exactly contrary to the schedule, and the scheduled selection funnel. What's the best way to come up to your speed, without incessantly pestering you with questions that distract you from your cutting-edge work, but not having to sift through a flood of opinion in the discussion forums? Any links not subject to discussion where I could start looking, while staying out of your way, would be best. Lots of stuff to see here. Still, move along. Don't mind the Fly on the Wall. Thanks.