For a design I'm working on for Tiny Tapeout, I need to tie all unused outputs to ground. What's the best way of doing this wrt to LVS? The easiest way would be to just strap them all across with a wire tied to ground, but this causes issues for extraction (pins shorted) and lvs.

When you say "causes issues", have you tried it with netgen since my Feb. 9 update to the netgen code? That should have resolved certain issues with shorted pins.

Let’s make sure that version of netgen gets into the precheck docker.

no not tried the new netgen yet

The other solutions: (1) If it's a digital signal, then add a

conb

cell and tie the signal to

LO

. (2) Add a metal resistor in the layout. Both of those solutions require matching components in both the netlist and layout. In particular, method (2) doesn't have any automation support and is a manual process.

the other option would be to add tielo (or tiehi in case you need a 1) cells into the schematic/layout. It adds a bunch of transistors but should help reduce sensitivity to ESD though for a test chip that may be less relevant

@Roel Jordans: That's what the

conb

cell does in sky130, and that's what I recommend for digital signals. There is also a

conb

cell in the HVL library that can be used for 3.3V high and low signals.

ah, good to know! I hadn't found it yet by that name 😅

I guess "conb" is supposed to be short for "constant bit" or something. I don't know why they wouldn't just call it "tiehi" and "tielo" like everyone else. . .

Hi Matt, this may be just a semantic thing with your expression; "tie unused outputs to ground". I am assuming that you are tying the inputs to ground and not the outputs to ground. Just double check to make sure no power is going to your unused devices that you are tying the outputs to ground. If you are tying the output of devices that are powered up, you just created a short to ground and a huge current draw from the supply rail.

@Larry Harris good catch! I think Matt is referring to the unused

io_out

signals which are actually inputs to the gpio cells. Leaving these unconnected can result in Hi-Z gate leaks in the

caravel_core

region. Interestingly, it appears that yosys will automatically connect unused output signals to ground when synthesizing (not with elaborating only). So if you have 2 synthesized macros with shared outputs, and one of the macros does not drive an output, your final signal will be shorted to ground. Your rtl simulation will work as expected, but not the gl simulation.

@Matt Venn I had the same issue on my SAR design. Added metal resistors and matched to schematic. See the latest version of https://github.com/wulffern/tt06-sar

@Tim Edwards with the latest netgen I get this report

Please be aware that netgen matches black boxes to anything with the same pins. If your source netlist is missing cells, it may still “pass” LVS, which is probably not what you want. You can search for

is a black box in the

in the lvs.report and

Matching pins

and

contains no devices

in the lvs.log. This will catch all the ‘X’ devices too, so you need to remove those from the output.

I think I've got it sorted, thanks mitch!