ArunKumar P.V
02/27/2024, 3:09 PMMatthew Guthaus
02/27/2024, 8:05 PMMatthew Guthaus
02/27/2024, 8:07 PMArunKumar P.V
02/28/2024, 12:30 AMPerforming simulation-based characterization with Xyce
Other tools:
drc, pex -> magic (8.3.462)
lvs -> netgen (1.5.271)
----------
Actually, it has ended now, but LVS has failed.
The run is for a single-port SRAM using sky130 and it looks like, there are already two issues raised on GitHub for similar LVS mismatches.
https://github.com/VLSIDA/OpenRAM/issues/217
https://github.com/VLSIDA/OpenRAM/issues/220ArunKumar P.V
02/28/2024, 12:56 AMmacros/sram_configs
folder
It seems like the issue is specific to SP RAM as DP RAM compilation for sky130 has no issues based on the examples that I tried
sky130_sram_1rw_tiny.py ==> Fails
sky130_sram_1rw1r_tiny.py ==> Completed without errors
Matthew Guthaus
02/28/2024, 1:38 AMArunKumar P.V
02/28/2024, 11:50 AM