I've heard that closer elements will have less variation. Is there any data on distance vs variation? Or just any useful intuitions or order-of-magnitude estimates? (sky130a)

Same-surround is more important than just "close". The further apart your devices are, the more they will be affected by variation across the wafer. However, the difference in nearby electric fields will be a larger effect. Optical effects (adjacent geometry) is the main reason for dummy devices on all sides to improve matching, but the effect of electric fields tends to stretch out an order of magnitude beyond optical effects.

Q1 So within my 10mm chipignite area, when I'm minimizing distances between things, I should ~only consider electric field issues? Q2 Does any of the tooling have decent simulation of electrical fields? The "Simulation from parasitic extracted layout netlist" section of the "Open Source Analog Design Flow" doc is empty haha. "Fastercap" and "FastHenry" is also mentioned. Q3 I assume there is no easy way for a newb to get intuitions about those effects? Any good videos or book chapters appreciated

Always assume that the monte carlo results are for circuits where the transistors are near each other, and they were placed using proper layout techniques for mismatch reduction. Assume the worst case. Some PDKs offer options to indicate that some transistors are further apart, to reflect that in monte carlo sims. Anyway, if you're not making circuits which rely heavily on matching, like current mirrors and differential pairs, it's not a strong issue. However, it's hard to find an analog circuit which doesn't.

I have seen too many conflicting opinions about what sources of mismatch are more or less important, and surprisingly many different opinions even about the order of magnitude. What most analog designers do is to keep in mind a list of the essential techniques for mitigating mismatch, and satisfy as many of them as possible. Dummy devices. Quadrature symmetry. Same surroundings. Larger devices when possible (mismatch varies by inverse square root of area).

Ok so it's more of a "follow best practices and don't be too clever" situation. I will keep that in mind.

@Luke Harold Miles, Marcel Pelgrom is well-known for publishing some influential papers on experimental characterization of device mismatch. If you look up "Pelgrom's Law" you'll find a bunch of literature if you want to read about it.

@Ryan Brandt: I know the 1989 paper very well. It was very influential around the time I was working on a Master's degree (1990-1992).

How cool! It's great to get to chat with folks with experience in analog IC design. I studied it a bit in school but never had the resources to go beyond the stages of design and simulation. Did you get the chance to tape out a design for your Master's degree?

@Ryan Brandt: Many! It was the golden age of chip design. . . Fabrication costs were amply covered by NSF grants, and I could pretty much tape out whatever I wanted to, whenever I wanted to. I helped to create a lab at Stanford with Mike Godfrey, sort of a spin-off of Carver Mead's group at Caltech, and we were studying subthreshold MOSFET behavior. The Vittoz-Enz FET model featured heavily, as did the Pelgrom paper. My first tapeout was a silicon cochlea design; Neal Bhadkamkar did the circuit design, and I did the layout. I have the photomicrograph from MOSIS framed and sitting on the bookcase behind me. Funding from NSF started drying up around 2000 or so, after I had finished my Ph.D., which was lucky timing. The drive to get back to where we were in the 1990s is what got me here to Efabless and the Caravel chip (Caravel is exactly the framework in which I would have liked to drop the silicon cochlea; we could have spent much more time doing the research instead of figuring out how to build padframes).

@Tim Edwards How exciting! I had no idea that the space has changed so much over the last few decades regarding the funding situation. That must have been quite the experience! It sounds like you had the opportunity to work with some very interesting people too, and come out with some works of art as well. Maybe even some functional silicon too haha. Do you have any advice on how to get started with the open-source tools available for analog IC design? I know this is the place for it, but I just joined the slack and am a little overwhelmed haha

@Ryan Brandt: For schematics, use xschem (see the #xschem channel). For simulation, use ngspice (get version 42 from sourceforge). For layout, either magic (see #magic) or klayout (see #klayout). For parasitic extraction, use magic. For LVS, use netgen. Check the Efabless YouTube channel for video tutorials on schematic and layout. The YouTube suggested links will take you to other good tutorials.