Another question is about Verilog-A and xschem. I don't know if there are open source digital simulators that also support Verilog-A. The ngspice SPICE simulator can simulate Verilog-A modules that are compiled into .osdi files and placed in a directory known by the simulator. A good example is the reram testbench also provided by xschem_sky130. Since the top level netlist is a regular SPICE netlist all I needed to do was to add the correct netlisting rule for the reram subcircuit. See the

tb_reram.sch

schematic. The

XR1

symbol is a subcircuit. The subcircuit instantiates the 'N... element that is a verilog-A primitive. This element calls a model that sets some parameter values and binds to a verilog-A module: •

XR1

--> subcircuit

sky130_fd_pr_reram__reram_cell

• subcircuit

sky130_fd_pr_reram__reram_cell

--> instantiates the '`N`' line with

sky130_fd_pr_reram__reram_model

model. • The

sky130_fd_pr_reram__reram_model

model sets some parameter values and binds to the

sky130_fd_pr_reram__reram_module

Verilog-A code. • The

sky130_fd_pr_reram__reram_module

code placed in a

<http://sky130_fd_pr_reram__reram_module.va|sky130_fd_pr_reram__reram_module.va>

file is compiled with

openvaf

and the generated .osdi file is placed in a place known by ngspice. • In the netlist there is a

pre_osdi

/path/to/sky130_fd_pr_reram__reram_module.osdi

that allows ngspice to link in the compiled module. Thread in Slack Conversation