Local power density and temperature response must be incorporated as part of chip architecture and design. Aggregated power alone is no longer a sufficient metric.

NNShim: Thermal Hotspots Simulation on ML Accelerators

Compact transformer based power combination techniques for millimeter‐wave CMOS power amplifiers

This thesis is not the result of one person’s lone fight against the world and it’s reckless handling of information. [PDF] Design of Reversible Computing Systems; Large Logic, Languages, and Circuits MK Thomsen - arXiv preprint arXiv:2309.11832, 2023 https://scholar.google.co.in/scholar_url?url=https://arxiv.org/pdf/2309.11832&hl=en&sa=[…]99440699:AFWwaebE2Nd177APD_8FyDCDQ4Ec&html=&pos=0&folt=cit This PhD dissertation investigates garbage-free reversible computing systems from abstract design to physical gate-level implementation. Designed in reversible logic, we propose a ripple-block carry adder and work towards a reversible circuit for general multiplication. At a higher-level, abstract designs are proposed for reversible systems, such as a small von Neumann architecture that can execute programs written in a simple reversible two-address instruction set, a novel reversible … • Cites: ‪Common Mistakes in Adiabatic Logic Design and How to Avoid …‬

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https://github.com/erikdebenedictis/Shift/tree/main For more information, please see revcomp.org

https://github.com/interplanetary-robot/Verilog.jl On the Wire type. This is a datatype that represents an indexed array of 3-value logic (1,0,X). To make your stuff look more verilog-ey, the "v" suffix for unit ranges is provided. Eg: •

Wire{6:0v}

is roughly equivalent to

wire [6:0]

•

Wire{12:1v}

is roughly equivalent to

wire [12:1]

• SingleWire is aliased to

Wire{0:0v}

, roughly equivalent to

wire

On wire arrays Do the natural thing and use the non-initializing

Array{Wire{<descriptor>}}(n)

constructor from Julia. Note that when transpiling to verilog, the wire arrays will be down-shifted by one to make them one-indexed (this feature may change in the future!). Currently, binary muxes are not supported. Gotchas: • Assigning to wire array member partials is not allowed: • my_array = Array{Wire{1:0v},1}(6) • my_array[1] = Wire(0b11,2) # <== this is OK. • my_array[2][1:0v] = Wire(0b11,2) # <== don't do this. • • Assigning wire array member partials with a function is not allowed: • my_array[3][1:0v] = some_verilog_module(some_input) # <== don't do this. Slack Conversation

https://onlinelibrary.wiley.com/doi/full/10.1002/cta.2921 Reconfigurable FIFO memory circuit for synchronous and asynchronous communication

@Mohammed Fayiz Ferosh has left the channel

Awesome AI for EDA https://ai4eda.github.io/ Slack Conversation

FYI, ChatGPT-plus (GPT 4.0, a.k.a. "the paid version") now has the capability to analyze images. I uploaded a screenshot taken from gtkwave of the output of a VCD file, and ChatGPT was able to perfectly describe what was going on in the image. That includes being able to tell that the gtkwave display had a hierarchical list of signals in the left-side window, that the display was indicating time of simulation and was in the middle of the simulation and zoomed in, and it was able to correctly identify the signal names in the display (with one minor misspelling). This opens up a vast capability to debug digital (and probably analog, and mixed-signal) systems by direct analysis of the waveforms. Amazing. Slack Conversation

Mabrains is a big believer in the open source movement for the CAD tools allowing the masses to have real access to learning and understanding of a complex technology. Mabrains is trying to improve the CAD tooling for chip design for the open source community. We have collaborated on developing PDKs for the different open source technologies. Recently, we have seen the need for an advanced Physical Verification tool for the community that could scale well with the advanced technology nodes will using advanced programming techniques to save both memory and computational power. We are seeking the support of the community for such a project. We have made a small POC example (External measurement only) for testing the capability of achieving an external check on one of the large designs in GF180MCU technology. Here are some of the numbers: • We were able to complete an external check with 38 million vertices in the design in about 4 minutes of run time on a flat design. • The GDS had around 60 million vertices in total. • We were able to store the necessary data in memory efficiently in about 5GB of memory footprint using flat design. • I ran this test on an i7 Intel processor on 6 Cores with 16GB memory on the laptop. With such performance that would enable our open source tooling to support smaller technologies like 90nm and downwards to 16nm, 14nm and so on. Mabrains will focus on building a tool suite that supports the following: • Advanced high performance DRC engine • Advanced high performance LVS engine • Advanced high performance R/C/CC extraction engine. We are asking the community if such tool would be an addition to the tool suite we already have and if we could crowd fund this activity. Appreciate if you could answer the poll to get feedback. Slack Conversation

Michael P. Frank Now available: Slides from my talk "Limits of CMOS and Prospects for Adiabatic/Reversible CMOS," presented at the Texas Symposium on Computing with Emerging Technologies (CoMET '23). Video to follow shortly. https://sandia.gov/app/uploads/sites/210/2023/10/Comet23-slides-topost.pdf

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Looks like Minimal Fab at AIST published an open source PDK! https://github.com/mineda-support/ICPS2023_5 Slack Conversation

https://chat.openai.com/g/g-Ag3GGHb4h-reversible-computing-tutor Reversible Computing Tutor. Expert in reversible computing with a comprehensive knowledge base. GPT/Bard to help people get started; also look through the materials on https://sandia.gov/ccr/staff/michael-p-frank/… and references they cite; some older research webpages are hosted on http://revcomp.info.

https://j-towns.github.io/papers/flipper-short.pdf ‘Flipper’ (available at github.com/j-towns/flipper) Verified Reversible Programming for Verified Lossless Compression James Townsend and Jan-Willem van de Meent University of Amsterdam Abstract Lossless compression implementations typically contain two programs, an encoder and a decoder, which are required to be inverse to one another. We observe that a significant class of compression methods, based on asymmetric numeral systems (ANS), have shared structure between the encoder and decoder—the decoder program is the ‘reverse’ of the encoder program—allowing both to be simultaneously specified by a single, reversible function. To exploit this, we have implemented a small reversible language, embedded in Agda, which we call ‘Flipper’ (available at github.com/j-towns/flipper). Agda supports formal verification of program properties, and the compiler for our reversible language (which is implemented as an Agda macro), produces not just an encoder/decoder pair of functions but also a proof that they are inverse to one another. Thus users of the language get formal verification ‘for free’. We give a small example use-case of Flipper in this paper, and plan to publish a full compression implementation soon.

The code defines several concepts such as

_<->_

(bidirectional functions), flippable syntax, parsing functions for various constructs, compilation functions, and proof-building functions. It also includes tests for various scenarios.

GPT --- Leveraging HOL (Higher Order Logic) Agda Flipper with nVidia ChipNeMo to create fully adiabatic PySpice circuits descriptions is a complex task that involves integrating multiple tools and technologies. The process can be broken down into several steps: 1. Understanding HOL Agda Flipper: - Familiarize yourself with HOL Agda Flipper and its capabilities. Understand how it handles bidirectional functions, pattern matching, and other features relevant to circuit descriptions. 2. Understanding nVidia ChipNeMo: - Learn about nVidia ChipNeMo, an open-source framework for neural module networks. Understand its capabilities, how it interfaces with neural networks, and its potential for use in hardware description. 3. Identifying Adiabatic Circuit Requirements: - Understand the specific requirements and constraints of adiabatic circuits. Adiabatic circuits are designed to operate with minimal energy dissipation, and their design involves specific considerations. 4. Integration with PySpice: - PySpice is a Python library for circuit simulation. Understand how to interface HOL Agda Flipper and nVidia ChipNeMo with PySpice. This may involve generating PySpice-compatible circuit descriptions from the higher-level descriptions used in Agda Flipper. 5. Building Adiabatic Circuit Descriptions: - Leverage the capabilities of Agda Flipper and nVidia ChipNeMo to build higher-level descriptions of adiabatic circuits. This could involve describing the behavior of adiabatic logic gates, flip-flops, and other components. 6. Code Generation and Translation: - Develop a mechanism to translate the high-level circuit descriptions into a format that can be used by PySpice. This could involve code generation, translation functions, or other methods to bridge the gap between the description languages. 7. Simulation and Verification: - Use PySpice to simulate and verify the behavior of the adiabatic circuits. Ensure that the energy dissipation is minimal and that the circuits meet the design requirements. 8. Optimization and Refinement: - Iterate on the design, leveraging the capabilities of HOL Agda Flipper and nVidia ChipNeMo to optimize and refine the adiabatic circuits. Consider feedback from simulations and adjust the design accordingly. 9. Documentation and Sharing: - Document the design process, circuit descriptions, and simulation results. This documentation is essential for collaboration and sharing the adiabatic circuit designs with the community. 10. Community Engagement: - Engage with relevant communities, forums, and researchers working on adiabatic circuits, PySpice, and related topics. Share your work, seek feedback, and contribute to the collective knowledge in the field. Keep in mind that the integration of different tools and technologies requires a deep understanding of each component. Additionally, working on adiabatic circuits may involve expertise in both hardware design and machine learning, making collaboration with experts in these fields beneficial.

https://github.com/alugupta/ACT/blob/main/tutorial/slides/pdf/ACT_MICRO_model.pdf About ACT An Architectural Carbon Modeling Tool for Designing Sustainable Computer Systems Slack Conversation

• Construct AI for EDA platform and introduce trained AI model to the EDA platform #generative-ai Slack Conversation

https://github.com/alugupta/ACT/blob/main/tutorial/slides/pdf/ACT_MICRO_model.pdf About ACT An Architectural Carbon Modeling Tool for Designing Sustainable Computer Systems Slack Conversation

OSCC/iEDA 从 Netlist 到 GDS 的开源芯片设计 EDA 平台