Art Scott
09/16/2023, 1:58 PMArt Scott
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09/28/2023, 10:08 AMArt Scott
09/28/2023, 10:37 AMWire{6:0v}
is roughly equivalent to wire [6:0]
• Wire{12:1v}
is roughly equivalent to wire [12:1]
• SingleWire is aliased to Wire{0:0v}
, roughly equivalent to wire
On wire arrays
Do the natural thing and use the non-initializing Array{Wire{<descriptor>}}(n)
constructor from Julia. Note that when transpiling to verilog, the wire arrays will be down-shifted by one to make them one-indexed (this feature may change in the future!). Currently, binary muxes are not supported.
Gotchas:
• Assigning to wire array member partials is not allowed:
• my_array = Array{Wire{1:0v},1}(6)
• my_array[1] = Wire(0b11,2) # <== this is OK.
• my_array[2][1:0v] = Wire(0b11,2) # <== don't do this.
•
• Assigning wire array member partials with a function is not allowed:
• my_array[3][1:0v] = some_verilog_module(some_input) # <== don't do this.
Slack ConversationArt Scott
09/28/2023, 11:19 AMMohammed Fayiz Ferosh
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11/11/2023, 2:09 PM_<->_
(bidirectional functions), flippable syntax, parsing functions for various constructs, compilation functions, and proof-building functions. It also includes tests for various scenarios.Art Scott
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11/26/2023, 1:43 PM