@Tim Edwards this works!

.subckt nand2_wrapper A B out
A1 [A B] out d_lut_sky130_fd_sc_hd__nand2_1
.ends

.subckt stdcells a_QLATCH a_A a_X a_B a_Y a_CLK a_Q a_RESET_B a_XSCHEM a_VCC a_VSS

...
AA2D1 [a_A] [A] todig_1v8
AA2D2 [a_B] [B] todig_1v8
...
...
XA1 A B IX nand2_wrapper
.ends
...
.model d_lut_sky130_fd_sc_hd__nand2_1 d_lut (rise_delay=200p
+ fall_delay=200p input_load=10f table_values "1110")

The netlist parser just flattens the hierarchy and doesn't care if subcircuit nodes are analog or digital. After netlist expansion the nand2 call (from subcirtcuit stdcells instantiated in top as X1):

a.x1.xa1.a1 [ x1.a x1.b ] x1.ix d_lut_sky130_fd_sc_hd__nand2_1

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