Hello , Currently I am trying to synthesize a bloc...
# openlanem
Maeesha Binte Hashem
01/22/2024, 9:24 PMHello , Currently I am trying to synthesize a block for 32 bit counter using OpenLAN and seeing this error : If anyone knows how to fix this please respond
w
Will S
01/22/2024, 9:25 PMCan I please see your config and verilog files
Will S
01/22/2024, 9:32 PMyou should also send the synthesis/linter.log file please
m
Maeesha Binte Hashem
01/22/2024, 9:43 PMokay sure
Maeesha Binte Hashem
01/22/2024, 9:47 PMthe config.json
Maeesha Binte Hashem
01/22/2024, 9:47 PMthe verilog file
Maeesha Binte Hashem
01/22/2024, 9:49 PMThis is synthesis/linter.log
w
Will S
01/22/2024, 9:59 PMyeah the problem is in your config file
Will S
01/22/2024, 9:59 PMDESIGN_NAME needs to be the name of the design top level
Will S
01/22/2024, 9:59 PMWill S
01/22/2024, 10:00 PMtry that and let me know
m
Maeesha Binte Hashem
01/22/2024, 10:01 PMokay trying
Maeesha Binte Hashem
01/22/2024, 10:02 PMOMG ! It's working !
Maeesha Binte Hashem
01/22/2024, 10:02 PMThank you so much ....I have been stuck with this problem for last 6/7 hours
Maeesha Binte Hashem
01/22/2024, 10:02 PMThanks a ton
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