Asokan
01/19/2024, 5:17 AMhtamas
01/19/2024, 6:16 AMassign io_in={a,b};
. In the module user_proj_and_gate
, the bus io_in
is an input from the outside and you are passing a
and b
to the submodule and_gate
. You might want to do the assignment the other way round.
You also have a typo in some of your variable names, and the assignments probably don't do what you expect as the bit widths don't match: io_in
is 3 bits but {a,b}
is 2 bits, also io_out
is 3 bits but y
is 1 bit. Finally you might want to change the value of io_oeb
to something different.Asokan
01/19/2024, 6:57 AMAsokan
01/19/2024, 6:57 AMMatt Venn
01/19/2024, 12:24 PMAsokan
01/19/2024, 12:27 PMMatt Venn
01/19/2024, 12:29 PMMatt Venn
01/19/2024, 12:30 PMhtamas
01/19/2024, 9:25 PM