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<@U05GF3APUTG> min resistance should measure when ...
# reram
r
@Akash Levy min resistance should measure when control phase is completed ? and when i given the reset in first pulse and when i read in vbl i can see that resistance is falling 200m/65n its very small resistance why? and every pw should be given of 200ns ?
a
Can you send a waveform image?
Pulse width is up to you. We used 200 ns in RADAR paper, but I have done as low as 10 ns in other ReRAM chips. On Skywater, I was able to get it working down to 20 ns. I’d recommend using >= 20 ns for the pulse width
Advantage of lower pulse width is obviously lower programming latency. Disadvantage is perhaps less reliable
Can I ask if you are just simulating or planning to get a chip manufactured?
r
@Akash Levy planning to get chip get fabricated
this is the wave form now i did reset then set to range 0 read pulse i did also i have question that sky water is limited to any algo for chip fab ? 2.how many pulse are required to store 30 pulse? 3.boundry min resistance should measure when control phase is completed ? 4.https://ieeexplore.ieee.org/document/6757457 for refrence resistor will this paper helps to know about placing the resistor in which side in circuit and usage that paper was refrence in RADAR paper 5. How is slope measurement useful i understood rmax measurement rmin at what point i need to measure i am confused
this is the waveform for control phase i did one blanket reset then 4 set and reset and one more set in last 2 set the resistance stop at 13k its not going down more it started from 43040k so i was assuming that control phase complete neeed to move to fine control phase range of n=0 5k rmax target i am correct? if i am correct than i am confused what certain pint would be my rmin to reach target and measure at what point rmax would be the final resistance to reach
a
your pulses look strange still. you are ramping the signals too slowly, which is why you have the diagonal lines. the lines should look almost vertical
Can you send me the PWL you are using?
we didn’t use an on-chip reference resistor, we measure it off-chip for RADAR chip
r
@Akash Levy hello i have attached the pwl pulse what i used could you please suggest the corrections , what do you mean by ramping slowly i think in vbl i just used 1 point as 0 when vsl used 10us increased pulse for reset that might be the reason of the diagnol pulse let me know where i am wrong and why resistance stop going down it got at 13k in control phase thank you and also could you please give answer for this also 1.sky water is limited to any algo for chip fab ? 2.how many pulse are required to store 30 pulse? 3.boundry min resistance should measure when control phase is completed ?
@Akash Levy.
a
None of these questions make sense to me. Why would skywater limit your algorithm during chip fabrication? What does it mean to “store 30 pulse”? You are not storing pulses. I don’t know what you mean by “control phase.” In general, I feel that it is hard to answer your questions when you appear to have an incomplete understanding of RRAM technology
r
@Akash Levy I am sorry my wording would be wrong I didn't mean storing pulse what I mean is that pulses required to program the reram for 3 bits per cell I am attaching the picture from the paper and thank you for letting me know about the skywater this is my first appearance to chip fabrication so I that question got in mind To know Rwmin there will be some point where after giving read pulse we will get know for that scenario could you say please Also could you also suggest the corrections in pulse for above
@Akash Levy For control phase I mean coarse control phase I have attached the picture and also above and highlighted the point Hope now my questions make sense
@Akash Levy.
a
I would not worry about the write algorithm right now. If you are planning to fabricate an array, I would implement the write algorithm off-chip (rather than in silicon). Then you can implement the algorithm with off-chip circuitry however you like (we did it in Python)
I would instead focus on getting a manufacturable array created and make sure that SET/RESET/READ will work properly on different cells/words
Especially since this is your first ReRAM chip, spending time on the write algorithm pre-silicon is a waste of time. The well-posed ReRAM models don’t properly capture the real amount of randomness you see in real devices.
r
@Akash Levy sorry couldnt reply because i was sick so in the past few days i tried changing every parameter and test but no change for the current for set pulses when i read using the read pulse could you give some suggestion please i have attached the waveform and also my advisor is suggesting me to first test with few pulses and see the changes in the current he said but i followed ISPP WAVEFORM also and i kept first reset then read-set-read-reset-read-set-read and also i tried Reset-read-set-read-set-read-set-read but no changes in current just 63n-64n it was i tried varying the VWL also for set but no change
a
These waveforms look quite a bit better. You probably need to tune the word line a little more carefully, using lower voltages during the write pulse. Also, as I said before, this model doesn’t capture the real device behavior perfectly
You should also plot the RRAM “gap” variable to see whether it is getting SET or not. BTW the SET appears to be happening on the first pulse, so you should reduce the VWL and increment it slowly
r
@Akash Levy thank you I will try to follow your suggestion
@Akash Levy i have done 1.can you please let me know about the rram gap is it the vbl in the plot for vbl input its vbl1? 2.i have given reset in the first pulse to reset to range 7 is it proper? 3.i have started incrementing the vwl for set 3.5, 4 then only 5 is this the reason of sudden spike in current ? 4.i have used the same for ns but it did not work when i used micro period it did why like that ? 5.i have attached the wave form and circuit picture 6.pulse name=VWL value="PWL(0 3 1u 3 1.5u 0 2u 2.5 2.5u 2.5 2.6u 0 2.7u 0 2.8u 0 3u 3.5 3.5u 3.5 4u 3.5 4.2u 0 4.4u 0 4.5u 0 4.6u 2.5 5u 2.5 5.1u 0 5.2u 0 5.3u 0 5.5u 0 5.6u 4.5 6.6u 4.5 6.7u 0 6.8u 0 6.9u 0 7.1u 0 7.2u 2.5 7.7u 2.5 7.8u 0 8u 0 8.2u 0 8.3u 5 9.3u 5 9.4u 0 9.6u 0 9.8u 0 9.9u 2.5 10.4u 2.5 10.5u 0 10.6u 0 10.8u 0 10.9u 0 11u 5 12u 5 12.1u 0 12.3u 0 12.4u 0 12.5u 0 12.6u 2.5 13u 2.5 13.01u 0 13.3u 0 13.5u 0 13.6u 5 14.6u 5 14.7u 0 14.9u 0 15u 0 15.1u 0 15.2u 2.5 15.7u 2.5 15.8u 0 16u 0 16.2u 0 16.3u 5 17.3u 5 17.4u 0 17.6u 0 17.8u 0 17.9u 2.5 18.4u 2.5 )" name=VSL value="PWL(0 2.5 1u 2.5 1.5u 0 2u 0 2.5u 0 2.6u 0 2.7u 0 2.8u 0 3u 0 3.5u 0 4u 0 4.2u 0 4.4u 0 4.5u 0 4.6u 0 5u 0 5.1u 0 5.6u 0 6.6u 0 6.7u 0 6.8u 0 6.9u 0 7.1u 0 7.2u 0 7.7u 0 7.8u 0 8u 0 8.2u 0 8.3u 0 9.3u 0 9.4u 0 9.6u 0 9.8u 0 9.9u 0 10.4u 0 10.5u 0 10.6u 0 10.8u 0 10.9u 0 11u 0 12u 0 12.1u 0 12.3u 0 12.4u 0 12.5u 0 12.6u 0 13u 0 13.01u 0 13.3u 0 13.5u 0 13.6u 0 14.6u 0 14.7u 0 14.9u 0 15u 0 15.1u 0 15.2u 0 15.7u 0 15.8u 0 16u 0 16.2u 0 16.3u 0 17.3u 0 17.4u 0 17.6u 0 17.8u 0 17.9u 0 18.4u 0 )" name=VBL value="PWL(0 0 1u 0 1.5u 0 2u 0.2 2.5u 0.2 2.6u 0 2.7u 0 2.8u 0 3u 2 3.5u 2 4u 2 4.2u 0 4.4u 0 4.5u 0 4.6u 0.2 5u 0.2 5.1u 0 5.2u 0 5.3u 0 5.5u 0 5.6u 2 6.6u 2 6.7u 0 6.8u 0 6.9u 0 7.1u 0 7.2u 0.2 7.7u 0.2 7.8u 0 8u 0 8.2u 0 8.3u 2 9.3u 2 9.4u 0 9.6u 0 9.8u 0 9.9u 0.2 10.4u 0.2 10.5u 0 10.6u 0 10.8u 0 10.9u 0 11u 2 12u 2 12.1u 0 12.3u 0 12.4u 0 12.5u 0 12.6u 0.2 13u 0.2 13.01u 0 13.3u 0 13.5u 0 13.6u 2 14.6u 2 14.7u 0 14.9u 0 15u 0 15.1u 0 15.2u 0.2 15.7u 0.2 15.8u 0 16u 0 16.2u 0 16.3u 2 17.3u 2 17.4u 0 17.6u 0 17.8u 0 17.9u 0.2 18.4u 0.2)" 7.in making lrs for range 0 and 1after reset pulse it takes several set pulses instead of gradual set and rest in radar right ? 8.can you please suggest from what range i should start vbl to what point for set i should increment and how many steps for increment ?
@Akash Levy.
a
1. By rram gap i just meant the v(xr2.nfilament) 2. Yes it looks like it is working. 3. You will see this if your pulse width is too long. I would try to reduce it. 4. I don’t understand your question… 5. ok 6. ok 7. Focus on ISPP not RADAR 8. Don’t increment VBL, it looks good the way it is. I would use shorter pulse widths for everything. For example, try changing all your “u”s in your PWL to “n”s and see what happens
r
@Akash Levy thank you I tried for n but there was no change in current I will try now with same pattern by replacing u with n
@Akash Levy I have been trying with every different values different combinations in vwl 16.50 micro current for all three set in picture why current is not changing any more ??
@Akash Levy 1.after 3 pulse in 4 pulse current is becoming microin begnning 3 pulses current is nano is it that set is happening in 4 pulse? if so then every 4 pulse has same current so please suggest what to do
I have tried with n by replacing u all the cuurent is in n its not becoming micro
@Akash Levy.
a
Ok, I will explain what is happening. In the example (before you change u to n), you are seeing the abrupt change in the filament state, where the SET happens almost instantly as you apply more and more pulses. This is not what happens in real life, you get a more gradual change. You have to remember that the Verilog-A model of the ReRAM is just a model to get you started, not a perfect representation of what you will see when you get back the silicon. This is why I previously suggested not spending so much time on getting the multiple-bits-per-cell programming working in simulation, since you told me you want to get a real chip. My suggestion to change u to n was just something to get you started. I was not implying that it will work, simply that decreasing the pulse widths by a factor of 1000x (microseconds to nanoseconds) will probably allow that abrupt transition to look more gradual. In my opinion, you are spending a lot of time on something (multiple-bits-per-cell ReRAM programming) that is best worth exploring when you have working silicon after the tapeout. There is so much other stuff you have to do to get working silicon that you do not seem to be looking at. In particular, you should be exploring (1) how to design an array of ReRAM cells, (2) how to design address/decoding circuitry, (3) how to design driver/readout circuitry. These things are so much more important if you are planning to get real silicon and it is very strange to me that you are asking me about the programming algorithm when you have nothing to program. I don’t have the bandwidth to keep answering your Slack questions. If you need more help with Skywater ReRAM, I am happy to set up a one-time meeting with you to discuss my suggestions for how to independently get started on building a multiple-bits-per-cell array. Let me know if that would help
r
@Akash Levy, thank you so much. I will work on your suggestions and collect any questions I have while working. I will get back to you to arrange a meeting.
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