Hello, I recently encountered an error in the floorplan, which indicates a maximum of 172 pins based on a certain area. I understand that increasing the 'DIE_AREA' can resolve this issue. However, I have doubts about how the maximum number of pins on the chip is determined based on the area provided. I tried calculating it using the values of 'FP_IO_VLENGTH', 'FP_IO_HLENGTH', 'BOTTOM_MARGIN_MULT', 'TOP_MARGIN_MULT', 'LEFT_MARGIN_MULT', 'RIGHT_MARGIN_MULT', and 'FP_IO_MIN_DISTANCE'. All these values are set to their default, and I still can't figure out how to reach the 172 pins. Here is my configuration file:

{
  "DESIGN_NAME": "parallel_RW",
  "VERILOG_FILES": "../../parallel_RW.v",
  "CLOCK_PORT": "clk",
  "CLOCK_PERIOD": 10,
  "FP_PDN_MULTILAYER": false,
  "FP_SIZING": "absolute",
  "DIE_AREA": "0 0 142 142"
}

If anyone could explain how to calculate the number of pins based on the area, I would be very grateful.

@Patricio Carrasco Looks like the

place_pins

routine in

openlane/scripts/openroad/ioplacer.tcl

handles pin placement. You can read more about the routine here and view the source code here.

@Mitch Bailey Thank you very much! I was reviewing, and a question came to mind regarding the margins. For example, BOTTOM_MARGIN_MULT has the description: "The core margin, in multiples of site heights, from the bottom boundary. If FP_SIZING is absolute and CORE_AREA is set, this variable has no effect." What does "site heights" refer to in this context? Do you have any information about these margins? Thank you in advance.

Just a guess, but

DIE_AREA

refers to the final size of your hardened design.

CORE_AREA

refers to the area filled with standard cells. The

MARGIN

refers to how far the

DIE_AREA

extends beyond the

CORE_AREA

in each direction. Site heights might refer to standard cell heights. So if you explicitly set your

DIE_AREA

and the

CORE_AREA

inside that, those settings will override any margin settings.