Hello, I'm currently working on creating a mixed-design circuit using OpenLane. I started integrating an analog circuit into a digital circuit a few days ago. I've encountered an issue, but I'm not know what it means. Could you help me understand it? Thanks.

Looks like

VDD_NETS

is not defined in your

config.json

file.

Something in your configuration file like this one below is needed for digital macros: set ::env(VDD_NETS) "vccd1" set ::env(GND_NETS) "vssd1" I am not sure about Analog macros but it could be sth like this: set ::env(VDD_NETS) "vdda1" set ::env(GND_NETS) "vssa1" Then you need macro hooks in top file where you instantiated your macros: An example: set ::env(FP_PDN_MACRO_HOOKS) "\ cpu vccd1 vssd1 vccd1 vssd1, \ memory vccd1 vssd1 vccd1 vssd1" You can check config parameter github page for definitions: https://github.com/The-OpenROAD-Project/OpenLane/blob/master/docs/source/reference/configuration.md

This error does not mention a problem in the definition of power, and it is not obvious. Now, I'm trying to define VDD and VSS

if that's a public project and you can share github repo, it will be easier for people to understand the problem and help otherwise it would be good to check config files for each macro and wrapper (top) module to say sth and Verilog instantiation templates (module definitions)

@Charly Meyer If you can share your

config.tcl

file, we might be able to offer some suggestions. One suggestion is to convert to

config.json

. Looks like you might be missing a space

set ::env(FP_PDN_MACRO_HOOKS)"AMUX2_3V VDD VSS VDD VSS"

should probably be

set ::env(FP_PDN_MACRO_HOOKS) "AMUX2_3V VDD VSS VDD VSS"

I'm trying to use the design I found here: https://github.com/praharshapm/vsdmixedsignalflow. I thought it is complete and I can use it directly.

Looks like a pretty old design. May not be compatible with the current flow.

the repo is last updated at Dec 2020. A lot of changes happened through the years and MPWs. I suggest cloning the latest openlane commit and install it. Then add your designs.

Do you have a Git example to share that includes the use of EXTRA_GDS_FILES? I have dificult to find one

You can check my github repo for config.tcl files: https://github.com/mbaykenar/openlane-designs Here in picosoc_method1 design, I instantiated different pre-hardened macros in the top file.

Thanks for the link. Just to run a test, I created a very simple design with an inverter and another component used like a black box. I corrected some issues, but when running the flow.tcl, I encountered an error at step 29 that I don't understand.

without looking at config file it is difficult to say sth, error says there is no mag file but the reason behind that error I can't predict

this is my config file

@Charly Meyer I don’t think the standard cells for sky130 are intended to be used as black boxes. The nwel/psub have separate connections. I also believe the power signals are VPWR and VGND unless you’ve manually changed them to VDD and VSS.

For the record, I used sky130 std logic cell library as blackbox for an FPGA fabric design, since I told OpenFPGA framework to use sky130 library to generate a netlist for FPGA fabric. Generated Verilog files instantiated sky130 logic cells, then in config file I needed to sky130 library path as black-box with: "VERILOG_FILES_BLACKBOX": [ "dir::../../dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v", "dir::../../dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v" ], But, in your config file, I did not understand why you defined VDD_NETS and GND_NETS two times. I don't know if it's ok or not, but to be in the safe side follow the example config files and use only one VDD_NETS and GND_NETS parameter in config file. Also I don't think you need to give extra lef, gds or lib files in config file if you are using sky130 logic cells. You can try removing extra lef and also using only 1 vdd_nets and gnd_nets parameters

I want use the same GDS file to be sure its size fit, but I changed the name.

as far as I know, if you instantiate a pre-hardened macro, then you need to give gds, lef and lib files, also define verilog file of the macro as black-box verilog file but if you want to instantiate sky130 std logic cells, then I added verilog files backbox as the files that I showed previously: primitives.v and sky130_fd_sc_hd.v, did not define gds, lef and lib in the config file, and that worked. then the circuit is important, is it a pre-hardened macro or a Verilog file instantiates sky130 std logic cells

To be more precise, my goal is to integrate an analog circuit with a digital circuit. I am experimenting with integrating a circuit as analog using an inverter. It is essential to use a LEF file, but I am unsure if a GDS file is necessary. The reason for using an existing circuit is that the ports and size are well defined.

@Charly Meyer You could look at some of designs from Dinesh like https://github.com/dineshannayya/riscduino.git They use hardened macros.

thanks 😉 I will check it