Hi team, i'm having problems when doing lvs over a cap_mim and a ppoly resistor. The following are the netlists generated by xschem and klayout

* cap_mim example
*****************

* Xschem
.subckt cap_mim_2f IN2 IN1
C1 IN2 IN1 cap_mim_2f0_m4m5_noshield c_width=5e-6 c_length=5e-6 m=1
.ends
.end


* Klayout

.SUBCKT cap_mim_2f IN2 IN1
C$1 IN2 IN1 5e-14 cap_mim_2f0_m4m5_noshield A=25P P=20U
.ENDS cap_mim_2f

* errors
Net IN2 is not matching any net from reference netlist
Net IN1 is not matching any net from reference netlist

* Resistor example
******************

* xschem
.subckt resistor_core IN2 IN1 B
R2 IN2 IN1 B ppolyf_u r_width=1e-6 r_length=1e-20 m=1
.ends
.end

* Klayout

.SUBCKT resistor_core B IN1 IN2
R$1 IN1 IN2 B 7000 ppolyf_u L=20U W=1U
.ENDS resistor_core

* Errors
Net IN1 is not matching any net from reference netlist
Net IN2 is not matching any net from reference netlist
Net B is not matching any net from reference netlist

I see that the only difference between the netlists is a extra number in the klayout extracted circuit. The commands I'm using to generate both are the following

xschem --rcfile ./xschemrc \
	--netlist \
	--netlist_path $(TOP_DIR) \
	--netlist_filename $(TOP).spice \
	--preinit 'set lvs_netlist 1; set spiceprefix 0' \
	--no_x \
	--quit

python $(KLAYOUT_HOME)/lvs/run_lvs.py \
	--variant=D \
	--run_mode=flat \
	--spice_comments \
	--verbose \
	--run_dir=$(TOP_DIR) \
	--layout=$(TOP_GDS) \
	--netlist=$(TOP_NETLIST_SCH) \
	--top_lvl_pins \
	--lvs_sub=B \
	--purge \
	--combine || true

I think the problem happens because I'm not using the right parameters. Which parameters should I use? @Amro Tork @Tim Edwards @Gabriel Maranhão @Mitch Bailey @

Sorry, I haven’t looked at klayout LVS yet. The extra extracted parameter is resistance in the resistor case and capacitance in the capacitor case. xschem is probably setup to create a netlist that will work with magic extraction. You probably need to either post process the spice file or modify the klayout comparison rules.

Hi David, thanks for your response. I don't think that klayout requires magic to make lvs, maybe xschem is not adding that resistance or capacitance in the netlist. Do you know which xschem variable adds it? I think @Stefan Schippers could clarify this problem

@aquiles viza: I think Mitch's point is that you would have better success using magic to do the extraction and netgen to do the LVS instead of klayout. Looks like klayout LVS still needs some work to be viable. The MiM cap extraction is wrong (the model uses c_width and c_length, not A and P), and it should not produce C and R values for the MiM cap and resistor, since those are not parameters of the model, or else for LVS purposes it should recognize them as being optional. In both cases, xschem is producing the correct output. Note that neither one of your netlists has a top level, and you have not specified any subcircuit names to match when running LVS, which might be the cause of the failure to match nets, but I don't use klayout for LVS, so I don't really know.

Now I understand, I though that Xschem-Klayout was the way to make lvs in gf180mcu since they are supported on efabless validation repo (fd_pv). I'm going to use Xschem-Magic instead.

I believe Klayout is working correctly. It doesn’t compare C and R values. Klayout itself requires C and R as dummy values which has no effect on the comparison as coded in the rule deck. And you don’t need to have them in your netlist at all from xschem side. Now, final note, Klayout automatically calculates A and P from L and W values to make it compatible with the comparison engine. There is a mismatch in the parameters names from L to c_length and W to c_width. It seems that this change on xschem side was done after the delivery of Klayout LVS

It seems that lvs on magic works for pmos, resistor, cap-mim only when the spiceprefix is added in xschem extraction. I don't know if I should be worried about the

Cell pin lists for cap_mim and cap_mim_2f altered to match.

but ignoring it, it's good.

@aquiles viza: The

altered to match

indicates that netgen thinks that between

cap_mim

and

cap_mim_2f

, the pins

IN2

and

IN1

are swapped between the schematic and layout, or in other words, that the tools disagree on which side of the MiM cap is the positive side and which is the negative. I don't have your layout and schematic, but otherwise I don't see anything obviously wrong in any of the tools, tool setups, or models.

@Amro Tork After converting L and W in the circuit extracted by klayout, should I run netgen lvs or klayout lvs? If is klayout lvs, How to avoid the generation of a new .cir? Maybe it in the other way, replace c_length and c_width on the netlist extracted with xschem. That makes more sense I think. I've tested this right now and works with cap_mim_2f0 but I'm still interested if there's a way to run klayout comparison engine without generating a .cir

@aquiles viza Did you manage to make a comparison without generating a new .cir file on Klayout during the LVS ? I tried to modify internally how Klayout was writing the .cir file, but I couldn't do it. Another way is to change only the capacitors on the schematic to fit the form used on Klayout extracted circuit, you did that?

@Gabriel Maranhão Please use the version that I have sent you.

@Gabriel Maranhão I'm using the efabless validation repo without modifying any file. When doing the xschem lvs netlist, I'm aplying some grep rules over it before making klayout lvs. See this makefile in lines 207 and 211