Hi, I am getting an error in Openlane in Klayout ...
# openlane
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Hi, I am getting an error in Openlane in Klayout step: "Streaming out GDSII with KLayout" The design is picorv32 from https://github.com/YosysHQ/picorv32 This is the error.log [ERROR]: during executing: "python3 /openlane/scripts/klayout/stream_out.py --output /openlane/designs/picorv32/runs/RUN_2023.12.28_07.40.34/results/signoff/picorv32.klayout.gds --lyt /home/aykenar/.volare/sky130A/libs.tech/klayout/tech/sky130A.lyt --lym /home/aykenar/.volare/sky130A/libs.tech/klayout/tech/sky130A.map --lyp /home/aykenar/.volare/sky130A/libs.tech/klayout/tech/sky130A.lyp --top picorv32 --with-gds-file /home/aykenar/.volare/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds --input-lef /openlane/designs/picorv32/runs/RUN_2023.12.28_07.40.34/tmp/merged.nom.lef /openlane/designs/picorv32/runs/RUN_2023.12.28_07.40.34/results/routing/picorv32.def |& tee /dev/null /openlane/designs/picorv32/runs/RUN_2023.12.28_07.40.34/logs/signoff/32-gdsii-klayout.log" [ERROR]: Exit code: 1 [ERROR]: Last 10 lines: Warning: No mapping for layer 'pwell', purpose 'LEFOBS' - layer is ignored Not a floating-point value: PIN (line=30662, cell=, file=picorv32.def) in Layout.read child process exited abnormally [ERROR]: Step 32 (gds_klayout) failed with error: -code 1 -level 0 -errorcode NONE -errorinfo { while executing "throw_error" (procedure "try_exec" line 15) invoked from within "try_exec python3 $::env(SCRIPTS_DIR)/klayout/stream_out.py --output $klayout_out --lyt $::env(KLAYOUT_TECH) --lym $::env(KLAYOUT_DEF_LAYER_MAP) --lyp ..." (procedure "run_klayout" line 22) invoked from within "run_klayout" (procedure "run_klayout_step" line 3) invoked from within "run_klayout_step"} -errorline 1 [ERROR]: Flow failed. I checked line 30662 in picorv32.def and it is: - vssd1 ( PIN vssd1 ) ( * VNB ) ( * VGND ) + USE GROUND These are some other lines above it: - vccd2 + USE POWER + ROUTED ; - vdda1 + USE POWER + ROUTED ; - vdda2 + USE POWER + ROUTED ; - vssa1 + USE GROUND + ROUTED ; - vssa2 + USE GROUND + ROUTED ; - vssd1 ( PIN vssd1 ) ( * VNB ) ( * VGND ) + USE GROUND + ROUTED met1 480 + SHAPE FOLLOWPIN ( 5520 484160 ) ( 481620 484160 ) I changed Verilog file (removed parameters and added as localparams) still has same error in the same line (this time line number is different) Regards, Burak