aquiles viza
12/27/2023, 3:39 PM# line 240
klayout-lvs-only: logdir xschem-lvs
python $(KLAYOUT_HOME)/lvs/run_lvs.py \
--variant=D \
--run_mode=flat \
--spice_comments \
--verbose \
--run_dir=$(TOP_DIR) \
--layout=$(TOP_GDS) \
--netlist=$(TOP_NETLIST_SCH) \
--top_lvl_pins \
--lvs_sub=B \
--combine || true
I have done lvs with the GUI, but it also fails.Farag Elsayed
12/28/2023, 6:59 AMaquiles viza
12/28/2023, 4:27 PMFarag Elsayed
12/28/2023, 4:53 PMpmos.spice
You have to extract lvs netlist from xschem instead of this one to be able to use it for klayout.
LVS netlist should be like this
** sch_path: /workspaces/DC23-LTC2-LDO/LDO/xschem/test/pmos/pmos.sch
.subckt pmos S D G
*.PININFO S:B D:B G:B
M2 D G S S pfet_03v3 L=0.7u W=5u nf=5 ad='int((nf+1)/2) * W/nf * 0.18u' as='int((nf+2)/2) * W/nf * 0.18u'
+ pd='2*int((nf+1)/2) * (W/nf + 0.18u)' ps='2*int((nf+2)/2) * (W/nf + 0.18u)' nrd='0.18u / W' nrs='0.18u / W'
+ sa=0 sb=0 sd=0 m=1
.ends
.end
M
Instead of XM
for FETs.aquiles viza
12/28/2023, 5:00 PMFarag Elsayed
12/28/2023, 5:02 PMaquiles viza
12/28/2023, 10:18 PMFarag Elsayed
12/30/2023, 12:52 AMr_width
with w
and r_length
with l
will solve your issue.Farag Elsayed
12/30/2023, 12:54 AM7000
represents the resistance value which has been ignored in the LVS comparisonaquiles viza
12/30/2023, 5:06 AMsed -i '/C.*cap_mim_2f0_m4m5_noshield/s/c_width/W/' $(TOP_DIR)/$(TOP).spice
sed -i '/C.*cap_mim_2f0_m4m5_noshield/s/c_length/L/' $(TOP_DIR)/$(TOP).spice