Can the GPIO pads set to 'analog' mode in open-frame Caravel chip produce a 100MHz output signal for VCO-based PLL design? @Tim Edwards, could you please share your insights on this?

The outputs are rated for 60MHz. You can get 100MHz output but not without significant attenuation. Yes, the Caravan analog pins are better suited for 100MHz operation but you will be responsible for your own ESD circuitry.

Thanks for the clarification. Is there any limit on max. current for GPIO pads in 'analog' mode ?

For the existing caravel chip, the analog connection was wired out of the GPIO pad with the digital router and is on minimum width metal wires, so that will be one limitation, although the 150 ohm ESD protection resistor is probably going to be the limiting factor.

So, the analog connection in GPIO pads also contains 150ohm series resistor. Is this for ESD protection purpose? Any option in GPIO to take out analog output without series resistor in between?

Do you care if the 100MHz output is voltage-mode like CMOS or current-mode like LVDS?

Want this 100MHz signal to be voltage mode to drive LO port of a mixer.

If it’s voltage-mode, your loss at 100MHz is only about half, assuming a single-pole roll-off with corner frequency at 60MHz: Gain @ 100MHz = 1/sqrt(1+(100MHz/60MHz)^2) = 0.514 If it were me I’ll probably drive this signal off chip differentially, then square it up with a high-speed comparator.

What would be the waveform shape, will it still retain its sinusoidal nature ?

If you feed in a sine wave you’ll get a sine wave out, with phase delay