Hello everyone Could somebody please explain why ...
# reram
r
Hello everyone Could somebody please explain why the filament behaves differently for 10 positive and negative pulses with pulse width modulation (pwl)? Additionally, I'm curious as to why the negative pulse output is consistently around 0, while the positive pulse output suddenly spikes after a certain amount of time.
a
Why is this behavior unexpected? SET tends to be abrupt as the filament connects the two electrodes (like a wire). At that point, the current will spike. RESET tends to be gradual and will result in low current (around 0). The RESET can happen in a few nanoseconds, which is on a time scale that is much smaller than what you are using as your pulse width right now (1 us). This also depends on the voltage you are using. I wouldn’t expect the behavior to look symmetric for SET and RESET because that is not what happens, either in the model or in reality.
r
@Akash Levy in above other messages I have read above the filament issue in that hyungjoo park replied there was issue with verilog patch file that has been updated in github I have use updated github repository but same result do you have any idea about that and also that means in my case do I have some error ?if so what could be the issue? Could you please provide clarity to me Thank you
a
@HyungJoo Park
h
Sorry for late response. Firstly, the issue I fixed was a convergence error due to the gradient burst of the exponential term of the verilog-a model. The behavior of the model does not changed. Secondly, the magnitude of the pulses you asserted is little bit smaller then I asserted(1.8V). I asserted 1.8V triangle pulses for SET and RESET, and 0.9V pulse for read operation.
r
@HyungJoo Park it's okay thank you so much in the above other thread I mentioned about the issue could you reply that please
h
I did. Please check