can i assign constants in the

user_project_wrapper

? i.e doing something like

assign la_data_out[63:32] = 'h0;

i only have a 32-bit signal that i want to attach, but with the constant assign i keep running into an LVS error that mentions that the

tiel

cell is missing its connections:

Net: VSUBS                                 |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__tiel/VPW = 1    |                                           
                                           |                                           
Net: TIE_ZERO_zero_/VSS                    |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__tiel/VSS = 1    |                                           
                                           |                                           
Net: TIE_ZERO_zero_/VDD                    |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__tiel/VDD = 1    |                                           
                                           |                                           
Net: TIE_ZERO_zero_/VNW                    |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__tiel/VNW = 1    |

even if i remove the constant assign, then it gets synthesised anyways (probably just implied) and i end up with the same LVS error

If you have

SYNTH_ELABORATE_ONLY: 1

, tying signals high or low is unlikely to work. Can you tie them at the the

user_proj_example

level?

Advice I've been given is, if necessary, have dedicated pins on your design (macro) that are vectors called

zeros

and

ones

that provide some 'spare' fixed

0

and

1

pins that you can wire up to things at the

user_project_wrapper

level. In my case, this was handy because I didn't want to have to reharden my macro, but DID want to potentially rewire it and change things like OEBs flexibly at the UPW level.

oh okay.. i do have

SYNTH_ELABORATE_ONLY: 1

, would it be troublesome if i set it to 0? otherwise, i'll try that

zeroes

and

ones

vector idea, seems like a nice solution for it

Setting

SYNTH_ELABORATE_ONLY: 0

will cause your top level to be synthesized and you probably want to add all the timing optimization settings, decap, fill, and diode insertion (something you might want to do, but it’s not a simple change).

ah gotcha, i won't do that then, sounds very complicated to get working

It’s not a one variable change. It would be nice to have two config templates for

user_project_wrapper

, one that just routes a hardened macro and one that does synthesis at the top level. The top level synthesis may be the only way to solve some timing errors.

yeah definitely, maybe it'll be a feature for later shuttles :) how come the user project can't be synthesised directly in the user project wrapper? is it due to some constraints for a die that large?

It can and there have been multiple tapeouts with the top level synthesized. It’ s just not the default. It may be as simple as removing all the settings preventing synthesis.

"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
        "VERILOG_FILES_BLACKBOX": [
                "dir::../../verilog/gl/user_proj_example.v"
        ],
        "EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
        "EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
        "EXTRA_LIBS": "dir::../../lib/user_proj_example.lib",
        "EXTRA_SPEFS": [
                "user_proj_example",
                "dir::../../spef/multicorner/user_proj_example.min.spef",
                "dir::../../spef/multicorner/user_proj_example.nom.spef",
                "dir::../../spef/multicorner/user_proj_example.max.spef"
        ],
        "FP_PDN_MACRO_HOOKS": "mprj vdd vss vdd vss",
        "QUIT_ON_SYNTH_CHECKS": 0,
        "FP_PDN_CHECK_NODES": 0,
        "SYNTH_ELABORATE_ONLY": 1,
        "PL_RANDOM_GLB_PLACEMENT": 1,
        "PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
        "PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
        "GLB_RESIZER_DESIGN_OPTIMIZATIONS": 0,
        "GLB_RESIZER_TIMING_OPTIMIZATIONS": 0,
        "PL_RESIZER_BUFFER_INPUT_PORTS": 0,
        "FP_PDN_ENABLE_RAILS": 0,
        "GRT_REPAIR_ANTENNAS": 0,
        "DIODE_INSERTION_STRATEGY": 0,
        "DIODE_ON_PORTS": "None",
        "RUN_HEURISTIC_DIODE_INSERTION": 0,
        "RUN_FILL_INSERTION": 0,
        "RUN_TAP_DECAP_INSERTION": 0,
        "RUN_CTS": 0,

of course, if you’re using other hard macros inside

user_proj_example

, you need to set the

EXTRA_LEFS

, etc. for those.