Can someone help me? I spent 3 days with it error

Looks like the

sm

instance isn’t connected to power. What does your physical hierarchy look like? What modules are you hardening?

@Mitch Bailey Yes. I saw. After trying a few configs and survey knowledge. I realized that I need to rewrite pdn.tcl to refactor the power grid to supply voltage to my macro (because pins vccd 1 and vssd1 are not connecting to metal layers 5 and metal 6). I tried with the pdn.tcl file (of OpenLane old version) but it doesn't match the new version of OpenLane. The error is described below. Can you help me rewrite pdn.tcl according to the new standard so I can arrange the power grid as I like. ERROR: OpenROAD 41a51eaf4ca2171c92ff38afb91eb37bbd3f36da This program is licensed under the BSD-3 license. See the LICENSE file for details. Components of this program may be licensed under more restrictive licenses which must be honored. [INFO]: Reading ODB at '/home/nam/edabk_new_project/efabless/caravel_user_project/openlane/synapse_matrix_design/runs/23_12_15_13_28/tmp/floorplan/6-tapcell.odb'… define_corners Typical read_liberty -corner Typical /home/nam/.volare//sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib read_liberty -corner Typical /home/nam/edabk_new_project/efabless/caravel_user_project/openlane/synapse_matrix_design/../../lib/RAM256.lib Using 1e-12 for capacitance... Using 1e+03 for resistance... Using 1e-09 for time... Using 1e+00 for voltage... Using 1e-03 for current... Using 1e-09 for power... Using 1e-06 for distance... Reading design constraints file at '/home/nam/edabk_new_project/efabless/caravel_user_project/openlane/synapse_matrix_design/runs/23_12_15_13_28/tmp/floorplan/3-initial_fp.sdc'… [WARNING STA-0367] derating factor greater than 2.0. Error: pdn.tcl, 30 TypeError in method 'microns_to_dbu', argument 1 of type 'double'

What does your physical hierarchy look like? What modules are you hardening?

What are the top metal layers on each hierarchy?

@Mitch Bailey Here is my project: EDABK-brain-soc I tried to fix it but no it didn't change the error. How do I reallocate my power grid to fit my design? Please help me.

@Nam Nguyễn Hồ Giang thanks for sharing your repo. Let’s start at the lowest level. Can you share the results for

make synapse_matrix_design

?

The DFFRAM block is using met4 so you can only have one level above that. Can you flatten

neuron_core_dffram

and

synapse_matrix_design

in

user_project_wrapper

and synthesize the top level instead of only elaborating? Are you planning on having multiple DFFRAMs?

Hi @Mitch Bailey. Thank you for your answer. In my design. I want to reuse

neuron_core_dffram

so I want to wrap it into the macro. I plan to use a lot of

neuron_core_dffram

in my design. Flattening the interconnection architectures will be done in

user_project_wrapper

. Is there a way for me to successfully flatten my design?

The gds for

synapse_matrix_design

seemed rather large. How many can you fit in the caravel

user_project_wrapper

area?

In the allowed Area, I want to fit as many

neuron_core_dfframs

as possible.

Ok, but your

synapse_matrix_design

is 2000x2000. Caravel openframe user area is only 3100x4700. The DFFRAM is 1100x500. You might be able to create the neuron_core_dffram with a top layer of met4 and then manually connect the DFFRAM power. You could then use openlane to connect several neuron_core_dfframs.

@Mitch Bailey Oh. The new

Caravel

increases the area for

users

, right? That's very good news for me. Previously, I used full flow completely automatically using OpenLane. So I don't know how to connect power to DFFRAM manually. I think the reason for the error in STEP PDN and IR DROP is that I am not providing manual power to DFFRAM, so the battery power is not connected • (if using the default automatic current, it will connect the power grid at

metal layer

6 and some in

metal layer 5

a while

caravel_user_project

only supports

metal layer 5

. I think that's my problem). It would be great if you could assist me in connecting the DFFRAM source and neron_core_dffram manually.

Try using a config file like this

{
  "DESIGN_NAME": "neuron_core_dffram",
  "DESIGN_IS_CORE": 0,
  "ROUTING_CORES": 1,
  "VERILOG_FILES": [
    "dir::../../verilog/neuron_core_dffram/synapse_matrix_design.v",
    "dir::../../verilog/neuron_core_dffram/neuron_core_dffram.v",
    "dir::../../verilog/neuron_core_dffram/neuron_block_design.v",
    "dir::../../verilog/neuron_core_dffram/neuron_parameters_design.v",
    "dir::../../verilog/neuron_core_dffram/neuron_spike_out_design.v",
    "dir::../../verilog/neuron_core_dffram/AddressDecoder.v"
  ],
  "CLOCK_PERIOD": 16.5,
  "CLOCK_PORT": "wb_clk_i",
  "CLOCK_NET": "sm.wb_clk_i",
  "FP_PDN_MACRO_HOOKS": "sram0 VPWR VGND VPWR VGND",
  "MACRO_PLACEMENT_CFG": "dir::macro.cfg",
  "FP_TAP_HORIZONTAL_HALO": 20,
  "FP_TAP_VERTICAL_HALO": 20,
  "FP_PDN_HORIZONTAL_HALO": 20,
  "FP_PDN_VERTICAL_HALO": 20,
  "FP_PDN_HSPACING": 30,
  "FP_PDN_VSPACING": 30,
  "FP_PDN_CORE_RING": 1,
  "FP_PDN_CORE_RING_VWIDTH": 5,
  "FP_PDN_CORE_RING_HWIDTH": 5,
  "FP_PDN_CORE_RING_VOFFSET": 14,
  "FP_PDN_CORE_RING_VSPACING": 1,
  "FP_PDN_VWIDTH": 5,
  "PL_RESIZER_SETUP_MAX_BUFFER_PERCENT": 50,
  "GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT": 50,
  "VERILOG_FILES_BLACKBOX": [
    "dir::../../verilog/gl/DFFRAM256x32.v"
  ],
  "EXTRA_LEFS": "dir::../../lef/DFFRAM256x32.lef",
  "EXTRA_GDS_FILES": "dir::../../gds/DFFRAM256x32.gds",
  "EXTRA_LIBS": "dir::../../lib/DFFRAM256x32.lib",
  "EXTRA_SPEFS": [
    "DFFRAM256x32",
    "dir::../../spef/multicorner/DFFRAM256x32.max.spef",
    "dir::../../spef/multicorner/DFFRAM256x32.min.spef",
    "dir::../../spef/multicorner/DFFRAM256x32.nom.spef"
  ],
  "FP_SIZING": "absolute",
  "DIE_AREA": "0 0 2700 2700",
  "MAX_TRANSITION_CONSTRAINT": 1,
  "MAX_FANOUT_CONSTRAINT": 16,
  "PL_TARGET_DENSITY": 0.3,
  "PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
  "GLB_RESIZER_SETUP_SLACK_MARGIN": 0.2,
  "GLB_RESIZER_HOLD_SLACK_MARGIN": 0.2,
  "PL_RESIZER_HOLD_SLACK_MARGIN": 0.4,
  "FP_PDN_HPITCH": 200,
  "MAGIC_DEF_LABELS": 0,
  "SYNTH_BUFFERING": 1,
  "RUN_LINTER": 0,
  "RUN_HEURISTIC_DIODE_INSERTION": 1,
  "GRT_REPAIR_ANTENNAS,": 1,
  "DIODE_ON_PORTS,": 1,
  "PL_ROUTABILITY_DRIVEN": 1,
  "FP_PDN_IRDROP": 1,
  "QUIT_ON_MAGIC_DRC": 0,
  "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
  "VDD_NETS": [
    "VPWR"
  ],
  "GND_NETS": [
    "VGND"
  ],
  "IO_SYNC": 0,
  "BASE_SDC_FILE": "dir::base_neuron_core.sdc",
  "RUN_CVC": 1,
  "pdk::sky130*": {
    "FP_CORE_UTIL": 30,
    "RT_MAX_LAYER": "met4",
    "scl::sky130_fd_sc_hd": {
      "CLOCK_PERIOD": 16.5
    },
    "scl::sky130_fd_sc_hdll": {
      "CLOCK_PERIOD": 10
    },
    "scl::sky130_fd_sc_hs": {
      "CLOCK_PERIOD": 8
    },
    "scl::sky130_fd_sc_ls": {
      "CLOCK_PERIOD": 10,
      "SYNTH_MAX_FANOUT": 5
    },
    "scl::sky130_fd_sc_ms": {
      "CLOCK_PERIOD": 10
    }
  },
  "pdk::gf180mcuC": {
    "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
    "CLOCK_PERIOD": 24,
    "FP_CORE_UTIL": 40,
    "RT_MAX_LAYER": "Metal4",
    "SYNTH_MAX_FANOUT": 4,
    "PL_TARGET_DENSITY": 0.45
  }
}

Change

macro.cfg

to place the sram macro.

Yes. Thank you for your support. I have flattened neuron_core

1. Caravel user project itself does not limit the number of layers. The process used is what limits the layers. The sky130A/B process is limited to 5 metal layers. When you say my design, are you referring to your macro? If that is the case, then in order to use your design as a hard macro in the openlane flow, I suspect you’ll be limited to 4 metal layers. 2. I think you’re using flattening as a synonym for hardening. I think flattening refers to the synthesis step of removing the soft macro hierarchy and hardening is creating a layout from the verilog definition which may contain either soft (with or without hierarchy) or hard macros or both. If your if you design contains a hard macro with metal4, the hardened output will use metal5. I do not know of a way to limit the hardened design to the same layer as the hard macro. 3. I think gate count usually refers roughly to the equivalent number of 2 nand gates (someone correct me it I’m wrong). I’m not sure how you can compute that from the metric.csv file. Precheck for

user_project_wrapper

runs CVC-RV which will give you device counts. You could add the number of mosfets (you probably don’t want diodes included), subtract the decap cells (x2 one pmos, one nmos) and divide by 4 (number of transistors in a 2 nand gate) to get a rough estimate for gate count.