Can someone help me with the LVS code error?, i check the power grid and all looks fine.

From what I can see, it looks like your verilog power connections may be incorrect.

Net: vss                                   |Net: vss                                   
  cby_2__1_/VGND = 2                       |  cby_2__1_/VGND = 2                       
  grid_clb/VGND = 4                        |  grid_clb/VGND = 4                        
  cbx_1__2_/VGND = 2                       |  cbx_1__2_/VGND = 2                       
  grid_io_top/VGND = 2                     |  grid_io_top/VGND = 2                     
  cbx_1__1_/VGND = 2                       |  cbx_1__1_/VGND = 2                       
  cbx_1__0_/VGND = 2                       |  cbx_1__0_/VGND = 2                       
  sb_2__2_/VGND = 1                        |  sb_2__2_/VGND = 1                        
  sb_2__1_/VGND = 1                        |  sb_2__1_/VGND = 1                        
  sb_2__0_/VGND = 1                        |  sb_2__0_/VGND = 1                        
  cby_1__1_/VGND = 2                       |  cby_1__1_/VGND = 2                       
  sb_1__2_/VGND = 1                        |  sb_1__2_/VGND = 1                        
  grid_io_bottom/VGND = 2                  |  grid_io_bottom/VGND = 2                  
  sb_1__1_/VGND = 1                        |  sb_1__1_/VGND = 1                        
  sb_1__0_/VGND = 1                        |  sb_1__0_/VGND = 1                        
  grid_io_right/VGND = 2                   |  grid_io_right/VGND = 2                   
  cby_0__1_/VGND = 2                       |  cby_0__1_/VGND = 2                       
  sb_0__2_/VGND = 1                        |  sb_0__2_/VGND = 1                        
  grid_io_left/VGND = 2                    |  grid_io_left/VGND = 2                    
  sb_0__1_/VGND = 1                        |  sb_0__1_/VGND = 1                        
  sb_0__0_/VGND = 1                        |  sb_0__0_/VGND = 1                        
                                           |  grid_clb/VPWR = 4                        
                                           |  grid_io_left/VPWR = 2                    
                                           |  gf180mcu_fd_sc_mcu7t5v0__tieh/VPW = 1    
                                           |  grid_io_right/VPWR = 2                   
                                           |  gf180mcu_fd_sc_mcu7t5v0__tiel/VSS = 1    
                                           |  grid_io_top/VPWR = 2                     
                                           |  grid_io_bottom/VPWR = 2                  
                                           |  sb_0__0_/VPWR = 1                        
                                           |  cby_0__1_/VPWR = 2                       
                                           |  sb_0__1_/VPWR = 1                        
                                           |  gf180mcu_fd_sc_mcu7t5v0__tieh/VSS = 1    
                                           |  sb_0__2_/VPWR = 1                        
                                           |  cby_1__1_/VPWR = 2                       
                                           |  sb_1__0_/VPWR = 1                        
                                           |  cbx_1__2_/VPWR = 2                       
                                           |  sb_1__1_/VPWR = 1                        
                                           |  cby_2__1_/VPWR = 2                       
                                           |  sb_1__2_/VPWR = 1                        
                                           |  gf180mcu_fd_sc_mcu7t5v0__tiel/VPW = 1    
                                           |  sb_2__0_/VPWR = 1                        
                                           |  cbx_1__1_/VPWR = 2                       
                                           |  sb_2__1_/VPWR = 1                        
                                           |  cbx_1__0_/VPWR = 2                       
                                           |  sb_2__2_/VPWR = 1

vss

is connected to both

VGND

and

VPWR

of the macros. Also, it appears that you’re trying to connect something to

tieh

and

tiel

at the top level, but have declared the

SYNTH_ELABORATE_ONLY

. This is causing the placement of the tie cells without connections to power rails and without power rails or fill cells. I think you can only use verilog high/low connections in hierarchies that are synthesized.

Net: VSUBS                                 |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__tieh/VPW = 1    |                                           
  gf180mcu_fd_sc_mcu7t5v0__tiel/VPW = 1    |                                           
                                           |                                           
Net: TIE_ONE_one_/VDD                      |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__tieh/VDD = 1    |                                           
                                           |                                           
Net: TIE_ONE_one_/VNW                      |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__tieh/VNW = 1    |                                           
                                           |                                           
Net: TIE_ONE_one_/VSS                      |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__tieh/VSS = 1    |                                           
                                           |                                           
Net: TIE_ZERO_zero_/VDD                    |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__tiel/VDD = 1    |                                           
                                           |                                           
Net: TIE_ZERO_zero_/VNW                    |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__tiel/VNW = 1    |                                           
                                           |                                           
Net: TIE_ZERO_zero_/VSS                    |(no matching net)                          
  gf180mcu_fd_sc_mcu7t5v0__tiel/VSS = 1    |

Can you share your top verilog?

HI @Mitch Bailey, i eliminated the

SYNTH_ELABORATE_ONLY

variable and it eliminate the mismatch TIE_ZERO_zero_, but i dont know why

vss

is connected to both

VGND

and

VPWR

This is the new lvs report, the top verilog file and the cby_2__1_ verilog file

If you eliminate

SYNTH_ELABORATE_ONLY

, you’ll probably need to enable fill/decap/tap cells and standard cell row pdn connections too along with timing optimizations and antenna repair. Right now,

PL_RANDOM_GLB_PLACEMENT: 1

which probably isn’t what you want for a large design. Your verilog appears to connect to submodule by position instead of by reference. Can you share your

verilog/gl/user_project_wrapper.v

file?

user_project_wrapper.v

Well that doesn’t match at all. It’s instantiating

user_proj_example

whereas your rtl had

grid_io_top_*

, etc. I bet the timestamp on the file is really out of date. May be openlane only copies the gl verilog if the flow completes successfully. Can you check your

28-*

files to determine the actual verilog used in the

lef.lvs

and share that?

Yes openlane only copies the gl verilog if the flow completes successfully. i follow your recommendation and change the config file, the LVS still happens, the

lef.lvs

file uses the instantiation of the top module:

Creating placeholder cell definition for module grid_io_bottom.
Creating placeholder cell definition for module grid_io_left.
Creating placeholder cell definition for module grid_io_right.
Creating placeholder cell definition for module grid_io_top.
Creating placeholder cell definition for module sb_0__0_.
Creating placeholder cell definition for module sb_0__1_.
Creating placeholder cell definition for module sb_0__2_.
Creating placeholder cell definition for module sb_1__0_.
Creating placeholder cell definition for module sb_1__1_.
Creating placeholder cell definition for module sb_1__2_.
Creating placeholder cell definition for module sb_2__0_.
Creating placeholder cell definition for module sb_2__1_.
Creating placeholder cell definition for module sb_2__2_.

I uses

"RUN_KLAYOUT_XOR":0,

in order to have a faster flow, just for test the LVS.

We need to check the gate level verilog used in LVS. Should be in

runs/<tag>/results/final/user_project_wrapper.v

or maybe in another of the

results

subdirectory, possibly with a

pnl.v

extension.

The gate level verilog files found in the final folder are the following: The vss and vdd signals are connected as shown in the image.

sb_0__0_ sb_0__0_ (.VGND(vss),
    .VPWR(vss),

This is the problem. I don’t know why it happens though. @Tim Edwards any ideas?

Not without a reproducible result.

after a carefully looking of the

lvs

reports, the

final verilog

file and the

pnl verilog

file i found the problem.