@Barak Hoffer @Stefan Schippers Has anyone tried the ReRam model with BE not bounded at GND? I got a convergence error when there was any component between BE and GND except for voltage sources.

Yes I confirm the same issue. I have a vsource- limiting resistor - reram cell loop that works. However putting the limiting resistor below the reram (so the reram BE terminal is no more at GND) causes convergence problems.

I found a solution, I will try to upload a fix over the weekend

I also found one. Changing the Implicit branch from (nFilament,BE) to (nFilament), which is identical to (nFilament, GND).

Yes, exactly.

HyungJoo Park Barak Hoffer can you please elaborate on the solution for this problem or upload an updated .va file?

The repository was updated with a fix by HyungJoo Park

where can i find that repository?