Hello, I have a few questions I'd like to ask: • 1. While trying to align LVS, it seems that the layout's SPICE recognizes four more devices compared to the SPICE from the schematic. I used 4 MOSFETs in the layout, and I'm wondering if it's possible for additional devices to be recognized due to interconnections. When examining the layout's SPICE file, it appears that the subcircuit of the MOSFETs I used might have generated these extra instances. I attempted to remove them, but it seems that the circuit doesn't match. Is there a way to prevent these from being created, or could the issue stem from another aspect? ** I've attached two SPICE files and the first figure showing the comp.out results. • 2. In the schematic's netlist, it seems that the order of pins following the MOSFET name indicates drain, gate, source, and body. However, in the layout's netlist, there are more pins generated. How can I understand the sequence here? Could the multiple pins be attributed to finger connections? **I've attached second figure • 3. After performing extraction to generate the SPICE file, I see diagonal white lines appearing in the layout, similar to the attached picture. It seems to signify an issue within my layout, yet I'm uncertain about the specific problem. When using 'feedback find,' errors like 'label attached to more than one unconnected node' or 'device missing 1 terminal' often appear. Clicking with 's' for the port seems to indicate proper connections, but I can't identify why these errors persist. **I've attached third figure I apologize for the scattered nature of my questions. If anyone has relevant information or helpful insights, I'd be tremendously grateful for any guidance provided.