Does anybody here happen to have a design (preferably one that has been taped out) with an LVDS receiver capable of 900Mbps?

hi @Tim Edwards, we don't have the design, but do you maybe have at least a general idea of a topology in mind? There is a group of students that I work with who have shown the critical amount of dedication that might be interested in the project.

The current ask is less of a project than trying to get a customer's chip out the door for Nov. 15th. In the longer term, though, yes, I'm interested in being able to offer LVDS or LVPECL. At the startup company where I worked 15 years ago, we developed a nice block that was a combination selectable LVDS, LVPECL, HCSL, differential CMOS, and two single-ended CMOS (I know we had one of these for outputs; I don't recall if the same block had inputs or if we had a separate block for differential inputs). Something like that would be nice to have.

Ok, well, we can't respond to the current ask, then. However, the long term interest might be something we can align with. I suggest we meet up for a short talk after November 15th, as I am a bit stressed out right now: my students worked on the design for over two months and now there's a danger it doesn't go through the tape out due to something we can't influence, really. I am feeling a bit like Columbus, but I don't have the egg. I hope efabless will overcome the issue on the platform.

We will get the design taped out. As I mentioned to somebody else recently, we will never reject a customer's design because of our own error on the platform. It is possible to shove a design through precheck manually. Extra effort on our end, but it works.

Hi @Tim Edwards, Thanks, this brings peace. Please refer to this thread for details https://open-source-silicon.slack.com/archives/C016HUV935L/p1699880412676769?thread_ts=1699612057.383259&cid=C016HUV935L ; namely, it's not only us and efabless in the pipe, there's also prof. @Hieu Bui who needs to integrate our design - I hope he can confirm he has seen this and goes through with integration and submits the die with our design included. Please, professor.