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OpenLane question: Can I somehow provide port numbers in the OL/OL2 flow so that the terminals in the extracted SPICE netlist are not all mixed-up? <@U020J2W6Q84> <@U016EM8L91B>

If you have a netlist for which you want to match the port order, the method in magic is to use `readspice` to read in the netlist while you have the layout loaded, and the pins in the layout will be matched to the netlist and the ports ordered to match.  There are similar methods to annotate layouts from other formats;  doing a `lef read` on top of a layout will annotate the ports with LEF pin properties like use and direction.

`readspice` should work with nothing more than a black-box entry for the subcircuit.

<@U016EM8L91B> good to know! :slightly_smiling_face: Magic is a treasure trove of features, documentation could be better :wink: <@U020J2W6Q84> any way to use this with `OL2`?

<@U016EM8L91B> Ever pondered to write the “Ultimate Guide for the Magic Power User” book?

<@U02UAUGSQ22>:  Nearly every day.  Once I nearly pulled the trigger on it. . .

<@U02UAUGSQ22> not without a custom step; integrating this into Magic.StreamOut is on the table tho 

<@U020J2W6Q84> That would be really helpful, currently this is a real pain when simulating SPICE netlists coming out of OL2 in an `xschem` testbench.

<@U02UAUGSQ22> Can you use a wrapper? For example,
Test bench top level would look like this and you’d just switch between `X0` instances.
```.subckt test_circuitA
X0 A B C D circuitA_wrapper
.ends

.subckt circuitA_wrapper A B C D
X0 A B C D circuitA_xschem
*X0 D C B A circuitA_extracted
.ends

.subckt circuitA_xschem A B C D
...
.ends

.subckt circuitA_extracted D C B A
...
.ends```
Or you could wrap the extracted circuit so it looks like a the source and switch includes
```.include xschem/circuitA.spice
* .include ext/circuitA.spice```
where `ext/circuitA.spice` is
```.subckt circuitA .....
* pin order the same as xschem
X0 ..... CircuitA_ext
* pin order from extracted file
.ends

.include ext/CircuitA_ext.spice ```

<@U017X0NM2E7>:  The point is that that shouldn't be necessary and that we have tools and methods to ensure that the order of subcircuit ports is consistent across views.  It's one thing to say that you can hand-edit a testbench of a circuit with four ports.  Try that with a circuit with 200 ports.

I understand that reordering ports is not something to do manually. My suggestion was to copy the subcircuit header from the extracted file, as is, and change it to an instance line in the wrapper. You wouldn’t need to reorder the ports since within a subckt, spice connects by name.

<@U017X0NM2E7> I think that would work, but I’ll wait until we have a proper procedure. One golden reference should be plugged into all the relevant places to have consistent port ordering everywhere :grinning: 