Hi what can cause openlane to generate a wrong lib file, I have a module with 20-bit width ports such as: output [0:19] chanx_right_out; After I hardened this module and instantiated in the wrapper, openlane give error in Synthesis step complaining about: "ERROR: Incompatible array type 'chanx_left_in' : bit_width=18, bit_from=0, bit_to=19" When I check the lib file it is written there: lu_table_template(template_1) { variable_1 : total_output_net_capacitance; index_1 ("0.00050, 0.00126, 0.00319, 0.00806, 0.02037, 0.05146, 0.13002"); } type ("chanx_left_in") { base_type : array; data_type : bit; bit_width : 18; bit_from : 0; bit_to : 19; } type ("chanx_left_out") { base_type : array; data_type : bit; bit_width : 18; bit_from : 0; bit_to : 19; } type ("chanx_right_in") { base_type : array; data_type : bit; bit_width : 18; bit_from : 0; bit_to : 19; } type ("chanx_right_out") { base_type : array; data_type : bit; bit_width : 18; bit_from : 0; bit_to : 19; } After I manually edit lib file by changing bit_width from 18 to 20 the flow passes I attached verilog, sdc and lib files for the related module