Hello, I'm running OpenLane flow for my design and...
# gf180mcu
y
Hello, I'm running OpenLane flow for my design and getting these error messages in Global Routing Resizer Timing Optimizations step:
[STEP 20]
[INFO]: Running Global Routing Resizer Timing Optimizations (log: ../home/yunus/caravel_user_project/openlane/fpga_core/runs/23_11_07_16_58/logs/routing/20-resizer_timing.log)...
[ERROR]: during executing openroad script /openlane/scripts/openroad/resizer_routing_timing.tcl
[ERROR]: Log: ../home/yunus/caravel_user_project/openlane/fpga_core/runs/23_11_07_16_58/logs/routing/20-resizer_timing.log
[ERROR]: Last 10 lines:
36# 0x00007F6BFADE2F1E in /lib64/libtcl8.5.so
37# Tcl_EvalEx in /lib64/libtcl8.5.so
38# Tcl_Eval in /lib64/libtcl8.5.so
39# sta::sourceTclFile(char const*, bool, bool, Tcl_Interp*) in openroad
40# ord::tclAppInit(Tcl_Interp*) in openroad
41# Tcl_Main in /lib64/libtcl8.5.so
42# main in openroad
43# __libc_start_main in /lib64/libc.so.6
44# 0x0000000000D3DC77 in openroad
child killed: segmentation violation
[ERROR]: Creating issue reproducible...
I didn't get what is wrong, can you help me? I will post my log in the thread
20-resizer_timing.log
v
crash should be filed as github issue in OpenLane repo with issue reproducible created inside run directory
👍 1
child killed, some times due to system RAM issue. How much RAM do you have?
y
16 gb+8 gb swap
I didn't trace the RAM usage but routing is finished in OpenLane which I installed standalone from caravel repo.
exact same circuit, only changed value of "FP_CORE_UTIL" variable
v
There is no issue with latest OpenROAD commit and it is not crashed. It is completing successfully resizer stage. Maybe try re-running the same.