@Tim Edwards, since you are here maybe I can ask you another question 😉️ To create a handy macro for the SRAM (with proper power stripes) I adapted the

config.tcl

from here https://github.com/efabless/caravel_mgmt_soc_gf180mcu/tree/main/openlane/gf180_ram_512x8_wrapper to a

config.json

. But I get an error during [STEP 2] Single-Corner STA:

Reading netlist '/home/leo/Dokumente/workspace-gf-mpw-1/leosoc-gfmpw-1/openlane/gf180_ram_512x8_wrapper/runs/23_11_07_16_24/results/synthesis/gf180_ram_512x8_wrapper.v'…
Error while reading /home/leo/.volare/gf180mcuD/libs.ref/gf180mcu_fd_ip_sram/verilog/gf180mcu_fd_ip_sram__sram512x8m8wm1.v:
Make sure that this a gate-level netlist not an RTL file
You can add the following comment '/// sta-blackbox' in the file to skip it and blackbox the modules inside if needed.
Error: /home/leo/.volare/gf180mcuD/libs.ref/gf180mcu_fd_ip_sram/verilog/gf180mcu_fd_ip_sram__sram512x8m8wm1.v line 49, syntax error, unexpected REG
child process exited abnormally

When I add

/// sta-blackbox

to the file, the flow completes succesfully. This approach is also suggested in the OpenLane docs: https://openlane.readthedocs.io/en/latest/reference/configuration.html#macros-chip-integration This means the modules inside

gf180mcu_fd_ip_sram__sram512x8m8wm1.v

are blackboxed. Does this have any implications timing wise?