For GFMPW-1, would a mixed-signal project like a P...
# analog-designt
Thomas Dexter
11/06/2023, 3:51 PMFor GFMPW-1, would a mixed-signal project like a PLL be possible to implement within the digital i/o constraint? My thought would be that all of the analog logic would be internal, but the output clock could still conform to digital i/o levels?
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Amro Tork
11/06/2023, 8:48 PM@Thomas Dexter It would be difficult to get high frequency output as I believe I/O have a limit on the max supported frequency which is in range 40MHz to 250MHz. I don’t recall the exact number. You might need to simulate the I/O circuit at your intended frequency. I’m interested to know more about your project.
Amro Tork
11/06/2023, 8:50 PMIf your question if you could do the entire design internal without I/Os then I believe it’s doable. But I’m not sure of the practical use case of such design. To keep the high frequency entirely inside the chip.
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Tim Edwards
11/06/2023, 10:08 PM@Thomas Dexter: There are relatively few cases where you can create an analog design with both digital inputs and outputs; the PLL is one such, and yes, it should be doable. The drawback is that you will not be able to pull out any internal analog signals for testing, so all testing of the analog will have to be inferred, treating the whole analog system as a black box.
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