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LVS_check.log

config.json

Screenshot from 2023-10-31 19-56-52.png

Hello!
Does anyone know why I might have LVS errors in precheck?

I attach the LVS precheck log and the user project wrapper configuration file.

The log file has
```LVS result:
Final result: 
Circuits match uniquely.
.
LVS Done.
Warning: device level LVS may be incomplete due to 2 unflattened cell(s): see /home/baungarten/Desktop/HW_TI_Encryption/precheck_results/01_NOV_2023___00_25_59/outputs/reports/lvs.unflattened```
If you open, `lvs.unflattened`, you’ll probably see your 2 macros - `aes_Trojan` and `des_Trojan`.
Currently, your `lvs/user_project_wrappper/lvs_config.json` file probably has the default
```        "LVS_VERILOG_FILES": [
                "$UPRJ_ROOT/verilog/gl/user_proj_example.v",
                "$UPRJ_ROOT/verilog/gl/user_project_wrapper.v"
        ],```
If your gate level verilog for these macros is in `verilog/gl`,

then then change this to
```        "LVS_VERILOG_FILES": [
                "$UPRJ_ROOT/verilog/gl/aes_Trojan.v",
                "$UPRJ_ROOT/verilog/gl/des_Trojan.v", 
                "$UPRJ_ROOT/verilog/gl/user_project_wrapper.v"
        ],```

lvs.unflattened shows:
```aes_Trojan is a black box in the source
des_Trojan is a black box in the source```
and "lvs/user_project_wrappper/lvs_config.json" shows:
```	"LVS_VERILOG_FILES": [
		"$UPRJ_ROOT/verilog/gl/user_proj_example.v",
		"$UPRJ_ROOT/verilog/gl/$TOP_SOURCE.v"
	],```
does the  $TOP_SOURCE.v isn't work? or why it happens now and in previos precheck didnt it?


I will try with it, but the precheck takes time.
```"LVS_VERILOG_FILES": [
                "$UPRJ_ROOT/verilog/gl/aes_Trojan.v",
                "$UPRJ_ROOT/verilog/gl/des_Trojan.v", 
                "$UPRJ_ROOT/verilog/gl/user_project_wrapper.v"
        ],```

Full device level LVS is a new addition to precheck.

You can leave the `$TOP_SOURCE` in the file. It’s the same thing.

lvs.log

It still give me the LVS error.

I changed the `lvs/user_project_wrappper/lvs_config.json` with:

```	"LVS_VERILOG_FILES": [
	        "$UPRJ_ROOT/verilog/gl/aes_Trojan.v",
                "$UPRJ_ROOT/verilog/gl/des_Trojan.v", 
		"$UPRJ_ROOT/verilog/gl/user_proj_example.v"
	],```
The message `Warning: device level LVS may be incomplete due to 2 unflattened` didn't appears.

What could be wrong?

You’re missing `user_project_wrapper.v`. Looks like there’s `user_proj_example.v` instead. `user_proj_example` isn’t used , is it?

Sorry, i try it yesterday at nigth and i didn´t see that mistake, let me run it again.

With the changes you mentioned, the precheck was performed correctly, Thank you.