Hi, although I labeled the pins, after the extraction for LVS I get the pin mismatch error.

Amirhossein zanjani

10/31/2023, 8:13 AM

Hi, although I labeled the pins, after the extraction for LVS I get the pin mismatch error.

Mitch Bailey

10/31/2023, 8:43 AM

@Amirhossein zanjani Just a guess here. Normally, the layout is on the left and the source is on the right. If you used xschem to create the schematic netlist, be sure to set

Simulation

LVS netlist: top level is a .subckt

before netlisting.

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