Hi, I connected the layout to wrapper pads, ran LVS, I got: Circuits match uniquely with port errors. The undriven pads could be the reason? everything looks fine in the log
t
Tim Edwards
11/03/2023, 12:31 AM
If it says there are port errors, then those should show up in the output.
a
Amirhossein zanjani
11/03/2023, 7:09 AM
This is the comparison log, I couldn't find where is the issue
m
Mitch Bailey
11/03/2023, 1:49 PM
@Amirhossein zanjani Looks like your top cell is
user_analog_project_wrapper_empty
. You’ll probably want to change that to
user_analog_project_wrapper
.
How are you creating the source side netlist? Is it from xschem?
How are you running LVS? Is this the precheck
lvs.report
output?
a
Amirhossein zanjani
11/03/2023, 1:59 PM
Yes, it is from xschem. The layout is manually connected to the wrapper (not openlane) and the file is netgen LVS log
m
Mitch Bailey
11/03/2023, 2:14 PM
Are you adding pins to the xschem netlist with
_uq?
suffices? You probably don’t want to do that. There is an extraction option you can use to connect disconnected nets that have the same text. It is dangerous, but the
user_analog_project_wrapper
is set up with disconnected nets that have the same text.
Instead of
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