Hi! I have a question regarding the programming of the instruction memory used by the PicoRV32, we are trying to run the SoC on a ZedBoard FPGA for testing purposes since we also have our own added user components. We are using a wishbone bus for bus communication. I believe that memory is located not on the PicoRV32 but on the SoC in the SRAM, is there a way to program the SRAM through the ZedBoard's ARM processor (which is an AXI bus protocol) or to flash the SRAM using the QSPI flash interface? I have looked at the caravel_board and from what I am understanding, the way it programs the caravel processor is by flashing the caravel processor through SPI flash.

First, the processor on Caravel is a VexRISC, not a PicoRV32 (since about two years ago). I am unclear what you are doing here. It sounds like you have taken the core processor, or a core processor, apparently the PicoRV32, and are trying to implement a full SoC on an FPGA. In that context, your question makes a bit more sense since the PicoRV32 code is written in a way that the memory can be instantiated within the PicoRV32 module or outside of it. In the Caravel implementation of the PicoRV32 (from MPW-one, or you could look at my much more recent Openframe example at https://github.com/RTimothyEdwards/caravel_openframe_project), the memory is an SRAM IP block outside of the picorv32 module, as you noted. However, the PicoRV32 (or the VexRISC) does not run programs off of the SRAM, it runs programs off of the SPI flash which it accesses through an SPI flash controller module. On the Caravel chip, there is a way to program the SPI flash by bypassing the processor and running SPI commands to the SPI flash directly from the housekeeping SPI, which is mainly just a way of avoiding having a separate programming interface on the board for the SPI flash.

I see, thanks!

no, you can't