https://github.com/efabless/caravel/blob/main/openlane/gpio_control_block/yosys_mapping.v hi all, i was curious - what is the purpose of this file. i was also trying to understand what is $__DFFSR__ i was looking to sky130 - if i could find it -> found nothing similar. also is it like some kind of variable -> if so, where is it set & what stage?

@Bharath G S: There was once a time in which if you created verilog of the type:

always @(posedge clk or posedge reset) begin
    if (reset == 1'b1) begin
        signal1 <= signal2
        ...

Then yosys would properly generate a flop with SET and RESET where SET = f(reset, signal2) and RESET = f(reset, signal2). That is, it's a flop that when in reset is just buffering the value "signal2". At some point, that was deprecated in yosys. The function exists in the yosys intermediate form gate ALDFF, which is a flop with "asynchronous data" input AD and a latch L input that latches the asynchronous data. Since ALDFF does not map to any flop in the standard cell libraries for sky130, its mapping has to be described in terms of multiple gates, namely a flop with SET and RESET and some extra logic driving SET and RESET in a way that maps to the L and AD inputs of the ALDFF gate.

@Tim Edwards thank you for a elaborate explanation