Hi, I am trying to use the wishbone bus to communi...
# caravela
Angela Cui
10/24/2023, 5:19 PMHi, I am trying to use the wishbone bus to communicate between the user module and RISC V processor. I was wondering about the behavior of the processor when a request is not completed immediately (o_wb_ack is not immediately high). Are writes/reads to the user area address blocking or nonblocking?
t
Tim Edwards
10/24/2023, 7:00 PMAll wishbone accesses will block the CPU until the peripheral signals
o_wb_acka
Angela Cui
10/24/2023, 7:01 PMThank you!
Angela Cui
10/24/2023, 8:16 PMIf the peripheral is stalling, will the CPU continue asserting the request over wishbone every cycle, or will the request only be asserted once?
m
Matt Venn
10/26/2023, 9:44 AMTry the wb simulation in verilog/dv/
Matt Venn
10/26/2023, 9:45 AMYou can change the example design to add a few clock cycles to the request and see what happens
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