Hi, I am trying to use the wishbone bus to communi...
# caravel
a
Hi, I am trying to use the wishbone bus to communicate between the user module and RISC V processor. I was wondering about the behavior of the processor when a request is not completed immediately (o_wb_ack is not immediately high). Are writes/reads to the user area address blocking or nonblocking?
t
All wishbone accesses will block the CPU until the peripheral signals
o_wb_ack
. The peripheral can claim as many clock cycles as it needs to complete the read or write.
a
Thank you!
If the peripheral is stalling, will the CPU continue asserting the request over wishbone every cycle, or will the request only be asserted once?
m
Try the wb simulation in verilog/dv/
You can change the example design to add a few clock cycles to the request and see what happens