Hi everyone, has anyone successfully used the second clock in Caravel (user_clock2) , alongside the 'main' wishbone clock (clk)? Does it function the same?

They are derived from the same base clock. If you aren't using the on-board DLL clock, then both the wishbone clock and the "user_clock2" are the same as the frequency at the "clock" pin. If you are using the DLL, then the "user_clock2" has an independent divider; e.g., you could run the DLL at 100MHz (10MHz board-level clock * 10), and divide that value by 4 for the core clock (25MHz) and have the "user_clock2" running at 50MHz (DLL clock divided by 2) or 100MHz (DLL clock divided by 1, or rather passed straight through). The purpose of "user_clock2" was to provide a potentially high-speed clock that can run faster than the SoC is rated for. If you run the SoC at 100MHz, the SoC will stop running and the wishbone clock may or may not work at all (since it's also just passing the clock through, I expect that the wishbone clock will contine to work, but the SoC definitely won't). If you use both clocks at the same time, you either need to make sure that the clocks don't interact with each other, or else always ensure that the DLL is set up such that the one clock is a multiple of the other, and then re-synchronize the slower clock to the faster one.

Thanks! The reason we are asking is because we are sharing the area with a user who has a large digital design, with multiple flip-flops switching at once, and they are worried about push/pull on the power input which may affect the other designs. They will hold their design in reset using the logic analyser, but we were wondering if their design could use the second clock and that clock be turned off while ours is running, so their design is not consuming power. Is this possible? Their design doesn't use the wishbone, just the LA. They've described it here: https://github.com/algofoogle/raybox-zero/blob/ew/doc/EWSPEC.md

Yes, I think that should work.

Hi @Tim Edwards , we are sharing our space with @Anton Maurovic who is looking to use the

user_clock2

. Do you know how to, in the firmware, turn off

user_clock2

whilst our

wbs_clk_i

is still running? John believes there was a schematic drawing of how the clock system worked, describing the DLL and what registers were used to do the settings for it, but we cant seem to find it now. Do you know if such a thing still exists?

G'day folks, in a simulation I think I've accidentally done this, but I'm not sure why it works (or whether it will work the same way in hardware). These are the firmware lines that seem to do it:

reg_hkspi_pll_ena = 1;
reg_hkspi_pll_source = 0b00001111;
reg_hkspi_pll_bypass = 0;

I'm simulating by wrapping a

caravel

instantiation inside a Verilog TB, then running a gate-level sim (it's just my user project that's the gate-level part) using cocotb/iverilog. When the last line executes, it seems

wb_clk_i

and

user_clock2

both glitch, then

wb_clk_i

starts clocking at about 5% slower than the external input

clock

. Meanwhile,

user_clock2

seems to stop. I was actually expecting the lines above would slow down

user_clock2

, not stop it. But if this is a way to do it... well, fine 🙂 But why does it work? The doco I was using is this (at the bottom): https://github.com/efabless/caravel/blob/main/docs/rst/digital_locked_loop.rst

@Anton Maurovic thats the Documentation we were after! 🙂

I wouldn't trust it though 🙂 2 years old, and @Tim Edwards I think that doco has the wrong description for the

reg_hkspi_pll_source

register... at least, compared to the diagram Ellen posted.

Oh ok, yes an updated documentation would be brilliant

Yeah, the doc I'm looking at I THINK has the

..._source

and

..._divider

registers swapped by mistake, but I can't be sure.