Hey all, we are getting the following error in the LVS stage of the tape-out precheck. A strange pin called

vccd1_uq3

has appeared in the

user_project_wrapper.gds.spice

netlist. It also appears in the

user_project_wrapper.gds.nowell.spice

netlist, along with another strange one called

vssd1_uq2

. However, we have no idea where these have come from: We have extracted both our hand drawn TOP_mixed.gds (before it was hardened into user_project_wrapper) and the final user_project_wrapper.gds from Openlane, and neither of these netlists contain that pin (nor can we see it in the layout etc). Any suggestions?

The

_uqX

suffixes come from running

extract unique

in magic. The whole idea of unique net names gets rather problematic. If you label a net, that becomes its name in extraction, but if you label two different nets with the same name, then they both get extracted to the same name and therefore become the same net whether or not they are connected.

extract unique

goes and finds any unconnected nets with the same name and then changes the names so that each one is unique. There are two problems with this: (1) The

extract unique

method is too aggressive; it does not consider the expansion of any subcells, so that if you have a wire in two pieces that are bridged across by the contents of a subcell, then the two pieces will get two unique names, even though it should be obvious that the net is continuous. (2) The top level cell has pins, and the pin names are probably meaningful in other cell views (like those coming from the schematic), and renaming pins with unique extensions will just cause LVS mismatches. The sky130 I/O power and ground pads have metal extending into the chip core from both sides of the pad, so they come out as two wires, with a gap in the middle (plus there are some power and ground nets that have multiple pins). So every VDD and VSS net has multiple unconnected pins in the wrapper. If you run

extract unique

on this, those pins will get the unwanted extensions that will cause LVS errors. That should be solvable by using

extract unique nottopports

instead of

extract unique

. You could also probably solve the issue by wiring the pins together in the wrapper cell, although that would be quite a nuisance.

Thanks for the explanation @Tim Edwards - unfortunately for us its the Efabless' Tape-out pre check script that uses Magic to extract the user_project_wrapper GDS, so I don't think there's any way to tell it not to use

extract unique

. I'll have a look in the layout, and see if I can wire the vdd nets together in any obvious places next week!

@Ellen Wood: Well, there is a way to tell the script not to use

extract unique

which is for me to fix it and make a pull request and then get the website maintainers to make the same change to the server.

Oh OK 🙂 Do you think that's a change worth making then? Is the

extract unique

method used (as opposed to the "standard" extraction) because you need to be quite aggressive for the pre tape out checks?

(Sorry for the delay in replying) Yes, I think that's probably the correct solution, although we'll probably want to make sure this works with multiple projects; if necessary, you might have to edit your local precheck script, prove that it works, then we'll manually push through the design for tapeout on our side while we fix the problem on our end.

Thanks @Tim Edwards :) Will do. I think the problem might be coming from copying up the

vccd1

and

vssd1

power ports from the pre-hardened digital .mag file, plus drawing new vertical

vccd1

lines ourselves over on the analog side, to power those devices. Different nets, same names! That pre-check job was for a test structure, but I imagine we will run into the same problem with our real chip, which should be going through the tape out pre-check in a few days.

@Ellen Wood there are currently 2 different extraction types in precheck, analog (default for

caravel_analog_project_wrapper

) and digitial (default for

caravel_project_wrapper

). The analog extraction type uses

extract unique nottopports

, while the digital type will give unique names to multiple texts not on the same net. In your

lvs/user_project_wrapper/lvs_config.json

file, you can force top net virtual shorts with

"EXTRACT_TYPE": "analog",