Hi all I was trying to run the caravel_user_project provided by efabless, the link to the github is https://github.com/efabless/caravel_user_project_analog/tree/main The documentation to this sample project is given in the link https://github.com/efabless/caravel_user_project_analog/blob/main/docs/source/index.rst Under the run full chip simulation section when I try to run the make verify-<testbench-name> command I get a permission denied error and when I run sudo make verify-<testbench-name> command I get the "no rule to make target" error. In the documentation they say that the verilog test-benches are under this directory verilog/dv, a screenshot of the same is attached below for your reference. The screenshot of the mprj_por folder is also provided. Can someone tell me why am I getting this error message and please do give provide me your valuable suggestions so that I am able to correct this error and move forward.

There have been reports that

make verify-mgmt_por

dooes not work. https://open-source-silicon.slack.com/archives/C01EX4ATEKF/p1696487354366399 or https://open-source-silicon.slack.com/archives/C02096M650E/p1676586848842409