Hi, I looked at schematics of the caravel board and the external clock frequency seems to be 10 MHz (image) I am trying to understand PLL and clocking management circuit inside Caravel. I only found info related to PLL in housekeeping-spi part of the Caravel documentation: https://caravel-harness.readthedocs.io/en/latest/housekeeping-spi.html By default, PLL bypass bit is set, so does that mean user area clock (wb_clk_i) runs at 10 MHz by default? If I want to change frequency to 2 MHz for example, which registers do I have to update and which values would be? There are PLL enable, PLL DCO enable, PLL trim, PLL output divider, PLL output divider (2) and PLL feedback divider registers and I am having difficulties to understand which of them should I update. You can also redirect me any link giving more detailed info about PLL and clocking. Regards,

Yes will run at 10M by default

That's right; the divider is connected to the DLL, not the external clock. For a slower external clock I would suggest importing a clock from off-board (input to pin xclk) and disabling the on-board oscillator at J6 (which puts the oscillator OUT to high-impedance so that you can drive xclk externally).

Tim, did you try Konrad's script yet? https://github.com/kbeckmann/caravel-pll-calculator

@Matt Venn: I did try it; it looks okay except it doesn't check the minimum/maximum possible frequency on the internal ring oscillator, so it can produce results that are way out of range (the example at the bottom of the page has the oscillator going at 192MHz, which I know it can't hit, at least not without boosting the 1.8V supply to uncomfortably high levels).

Thanks for the answers and clarification 👍