Hi, I'm using yosys to generate a spice from a verilog file in gf180mcuC but I'm having problems to simulate a testbench using the generated spice file since ngspice complains that there are too few nodes in "gf180mcu_fd_sc__mcu7t5v0___clkinv_1". This is the script that I'm using:

set lib_path "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/gf180mcu_fd_sc_mcu7t5v0/liberty/gf180mcu_fd_sc_mcu7t5v0__tt_025C_3v30.lib"
yosys read_liberty -lib $lib_path
yosys read_verilog -sv SAR_Logic.v Code_Register.v Sequencer_Register.v
yosys synth -top SAR_Logic
yosys dfflibmap -liberty $lib_path
yosys abc -liberty $lib_path
yosys write_spice -top SAR_Logic sar_logic.spice

This is the line in the generated spice where ngspice reports the error

X0 rst 1 gf180mcu_fd_sc_mcu7t5v0__clkinv_1
X1 1 shift_register_out.12 2 gf180mcu_fd_sc_mcu7t5v0__nand2_1

and this is the definition of the cell in the pdk

.SUBCKT gf180mcu_fd_sc_mcu7t5v0__clkinv_1 I ZN VDD VNW VPW VSS
X_i_0 ZN I VSS VPW nfet_06v0 W=4.8e-07 L=6e-07
X_i_1 ZN I VDD VNW pfet_06v0 W=1.22e-06 L=5e-07
.ENDS

It looks like yosys isn't considering the power supplies and bulks in the spice, I'm missing something?

There may be a verilog option to add power nodes. If not, you might be able to write a script to do it or manually edit the file.