Hi, Do I have to connect all power lines in the top module (e.g user_project_wrapper), even if I only need 1 VDD and 1 VSS? Now Caravel has 4 VDD and 4 VSS lines by default (2 VDD, 2 VSS for analog). I only want to connect 1 VDD 1 VSS, since I have a lot of small hardened macros (60x120 and 120x60 and 120x120) instantiated in the top module (an eFPGA IP). With the default power configuration (H/VPITCH 180, H/VOFFSET 5, H/VWIDTH 3.1, H/VSPACING 3.1*5) macros do not cover, span the needed VDD and VSS. If I have 1 VDD and 1 VSS with pitch a value such as 40, then macros will reside both VDD and VSS. I checked caravel_ibex repo and it has 90 PITCH value with only a total of 4 power lines going vertical or horizontal instead of 8 for example:

@Burak Aykenar the solution to the macro_hook problem is in the issue you quoted. Add a

,

before the closing

"

on each line except the last. As to your previous question, The outer power ring met4 on the left and right of the pr boundary and the horizontal met5 on the top and bottom of the pr boundary needs to remain the same, but you can change the other met4 and met5. So you should be able to do just vssd1/vccd1 with a tighter pitch.

thanks, I applied power as only 1 vssd1/vccd1 pair with different pitch values and it passed PDN stage. I have LVS errors but I will open another threads since I think it's related to power connections of small macros