Hi, Do I have to connect all power lines in the t...
# openlane
b
Hi, Do I have to connect all power lines in the top module (e.g user_project_wrapper), even if I only need 1 VDD and 1 VSS? Now Caravel has 4 VDD and 4 VSS lines by default (2 VDD, 2 VSS for analog). I only want to connect 1 VDD 1 VSS, since I have a lot of small hardened macros (60x120 and 120x60 and 120x120) instantiated in the top module (an eFPGA IP). With the default power configuration (H/VPITCH 180, H/VOFFSET 5, H/VWIDTH 3.1, H/VSPACING 3.1*5) macros do not cover, span the needed VDD and VSS. If I have 1 VDD and 1 VSS with pitch a value such as 40, then macros will reside both VDD and VSS. I checked caravel_ibex repo and it has 90 PITCH value with only a total of 4 power lines going vertical or horizontal instead of 8 for example:
I think, changing VDD_NETS and GND_NETS config parameters with FP_PDN_H/V* parameters would be enough, but I am not sure and comfortable with these changes since I don't know well about power distribution constraints
https://github.com/The-OpenROAD-Project/OpenLane/issues/1518 possibly I have macro_hook problem in JSON file as states in this issue
m
@Burak Aykenar the solution to the macro_hook problem is in the issue you quoted. Add a
,
before the closing
"
on each line except the last. As to your previous question, The outer power ring met4 on the left and right of the pr boundary and the horizontal met5 on the top and bottom of the pr boundary needs to remain the same, but you can change the other met4 and met5. So you should be able to do just vssd1/vccd1 with a tighter pitch.
b
thanks, I applied power as only 1 vssd1/vccd1 pair with different pitch values and it passed PDN stage. I have LVS errors but I will open another threads since I think it's related to power connections of small macros
if someone comes into this thread to look for how to connect only 1 digital power pair to his design instantiated in the wrapper module, one needs to add pdn_cfg.tcl script in config.tcl or config.json https://github.com/The-OpenROAD-Project/OpenLane/blob/7ea7a2aeef4bea5445d133c26ca2b3e9f0d0c78f/scripts/openroad/common/pdn_cfg.tcl#L4 as "FP_PDN_CFG": "dir::pdn_cfg_tcl", In config.json, you have to add VDD and GND nets as: "VDD_NETS": [ "vccd1", "vccd2", "vdda1", "vdda2" ], "GND_NETS": [ "vssd1", "vssd2", "vssa1", "vssa2" ], and connect only vccd1 and vssd1 to your circuit with: "FP_PDN_MACRO_HOOKS": [ "your_module_inst1 vccd1 vssd1 vccd1 vssd1,", "your_module_inst2 vccd1 vssd1 vccd1 vssd1," ],