Hi, I was wondering for rtl verification of macros...
# caravelq
Qi Yang Lim
09/27/2023, 1:53 PMHi, I was wondering for rtl verification of macros & full chip simulation of caravel:
1. if our team has run & passes our own verilog testbenches, is it required to write and run our own cocotb testbenches on macro-level? (if yes hope you can point us to some materials on cocotb verification)
2. what’s the difference between the cocotb and the testcases (la_test1, la_test2 etc.) at full chip level simulation?
m
Matt Venn
09/28/2023, 8:02 AMHi Qi, I'm just learning this myself, so not 100% sure.
Matt Venn
09/28/2023, 8:02 AMfull chip simulation is strongly advised because a lot of people in the past have not connected their designs correctly
Matt Venn
09/28/2023, 8:02 AMthe cocotb testing is an alternative to the 'normal' verilog testbenc
Matt Venn
09/28/2023, 8:03 AMhave a look here for docs: https://caravel-sim-infrastructure.readthedocs.io/en/latest/index.html
Matt Venn
09/28/2023, 8:03 AMyour second question, the cocotb tests are new, and act as a demonstration of the system
q
Qi Yang Lim
09/28/2023, 9:31 AMHi Matt, thanks for your reply! I’ll look into the link you sent as well
m
Matt Venn
09/28/2023, 9:32 AMSo far I'm unable to run any of the cocotb tests, have you had any success?
q
Qi Yang Lim
09/28/2023, 9:42 AMNo as well, our team is looking at ways to learn about it and modify it to fit our system. But we have not successfully implemented cocotb tests
m
Matt Venn
09/28/2023, 12:51 PMwhat happens if you run
caravel_cocotb -t hello_worldq
Qi Yang Lim
09/29/2023, 9:40 AMWe haven’t reached that point yet, so I can’t provide you an answer. Currently facing some python environment setup issues, so tryna solve that right now.
2 Views