Hi, I was wondering if the print in the blinky running example goes to the FDTI chip https://github.com/efabless/caravel_board/blob/main/firmware/chipignite/blink/blink.c#L134 (if so.. at what baud rate can it be expected? )

Maybe it is 9600 at 10MHz core_clk ? It is my understanding the baud rate divisor is locked in the hardware design, maybe 20MHz and 40MHz core_clk is possible and provides x2 and x4 bauds rates. Maybe this area is the 32bit overflow counter method that sets the rate used https://github.com/efabless/caravel_mgmt_soc_litex/blob/main/verilog/rtl/mgmt_core.v#L6946C65-L6946C76

So I can confirm that the sample code does output the data over serial (9600 baud rate) on pins mprj_io[6] ser_tx , mprj_io[5] ser_rx and also on J4. I did not observe the data over the FTDI chip, did try to pull down on J2 but I think the FDTI chip might need more configuration?

Did you setup the gpio_control default direction, particularly for the UART TX as by default it maybe setup as input. Can't help with FDTI matters, what PCB design provides that chip on board ?

This is the caravel-dev-v5-M.2 caravel board https://github.com/efabless/caravel_board/tree/main/hardware/development/caravel-dev-v5-M.2 . I did not setup the FTDI chip and I am indeed guessing that there might be a problem there, the FTDI chip is used for programming using https://github.com/efabless/caravel_board/blob/main/firmware/chipignite/util/caravel_hkflash.py (under WSL2) and an UART /dev/ttyUSB0 (Linux kernel side)

did you ever solve this?